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Patent US3743855A successfully refreshed from Google Patents.
US3743855A
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Fault detecting and fault propagating logic gate
Assignee: Allen Bradley Co LLC
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Filing: 1971-06-10
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Granted: 1973-07-03
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Expires: 1991-06-10
Abstract
Abstract A logic gate has a fault sensing circuit connected to each of its input terminals and connected to actuate a switching means that open circuits the gate output terminal when there is no current flow either into or out of each gate input terminal. A first embodiment includes a photosensitive type current sensing circuit connected to the input terminal of a NOT gate. When a fault occurs at this terminal, a switching transistor actuates to turn off two drive transistors in a buffer circuit, which open circuits the output terminal. A second embodiment is similar but includes a transistor type current sensing circuit connected to the input terminal of a NOT gate. A third embodiment includes two fault sensing circuits connected to each of two input terminals of a NAND gate. Each fault sensing circuit connects to turn off the two drive transistors in a buffer circuit when a fault occurs at either input terminal. And finally, a fourth embodiment includes a fault sensing circuit connected to each of two input terminals of an AND gate, each circuit connected to deenergize a relay coil which opens a switch in the gate output terminal when a fault occurs at either input terminal.
Inventors
- 👤 O Struger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; B; B60; B60R; B60R22/00; B60R22/48; H03K19/007
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
79 words
In a logic gate having an input terminal adapted to receive a logic signal and an output terminal adapted to generate a logic signal in response to the logic state of the logic signal received at said input terminal, the improvement comprising: circuit means connected to said gate input terminal and said gate output terminal, said circuit means being operable to open circuit said gate output terminal in response to a malfunction condition sensed at said gate input terminal.
Claim 2
Dependent Claim
79 words
In a logic gate having an input terminal adapted to receive a logic signal and an output terminal adapted to generate a logic signal in response to the logic state of the logic signal received at said input terminal, the improvement comprising: circuit means connected to said gate input terminal and said gate output terminal, said circuit means being operable to open circuit said gate output terminal in response to a malfunction condition sensed at said gate input terminal.
Claim 3
Dependent Claim
37 words
The logic gate as recited in claim 1, wherein said circuit means includes: a fault sensing circuit connected to said gate input terminal; and switching means connected to said fault sensing circuit and said gate output terminal.
Claim 4
Dependent Claim
50 words
In a logic controller comprised of a plurality of logic gates having input terminals and output terminals interconnected, the improvement comprising circuit means associated with each logic gate to detect an open circuit at any one of its input terminals and propagate that open circuit condition to its output terminal.
Claim 5
Dependent Claim
50 words
In a logic controller comprised of a plurality of logic gates having input terminals and output terminals interconnected, the improvement comprising circuit means associated with each logic gate to detect an open circuit at any one of its input terminals and propagate that open circuit condition to its output terminal.
Claim 6
Dependent Claim
64 words
The logic controller as recited in claim 3 wherein the circuit means associated with each logic gate includes: a fault sensing circuit connected to detect an open circuit condition at a gate input terminal; and switching means connected to said fault sensing circuit and operable to open circuit the gate output terminal in response to an open circuit detected by said fault sensing circuit.
Claim 7
Dependent Claim
100 words
A logic gate having an output responsive to the logic state applied to an input, the combination comprising: a buffer circuit connected to said gate output and coupled to said gate input, said buffer circuit adapted to drive said gate output to a logic state in response to a logic state applied to said gate input; and a fault sensing circuit connected to said gate input and said buffer circuit, said fault sensing circuit operable to detect an open circuit condition at said gate input terminal and in response thereto drive said buffer circuit to open circuit said gate output.
Claim 8
Dependent Claim
100 words
A logic gate having an output responsive to the logic state applied to an input, the combination comprising: a buffer circuit connected to said gate output and coupled to said gate input, said buffer circuit adapted to drive said gate output to a logic state in response to a logic state applied to said gate input; and a fault sensing circuit connected to said gate input and said buffer circuit, said fault sensing circuit operable to detect an open circuit condition at said gate input terminal and in response thereto drive said buffer circuit to open circuit said gate output.
Claim 9
Dependent Claim
83 words
The logic gate as recited in claim 5, wherein the fault sensing circuit includes a current sensing circuit connected to said gate input and an electronic switch circuit connected to said current sensing circuit and said buffer circuit, the current sensing circuit being responsive to actuate said electronic switch circuit when there is no current flowing into or out of said gate input, and said electronic switch circuit being responsive when actuated to drive said buffer circuit to open circuit said gate output.
Claim 10
Dependent Claim
71 words
The logic gate as recited in claim 6 wherein said current sensing circuit comprises: an illuminating device connected in circuit with said gate input; and a photosensitive element positioned to receive light from said illuminating device and adapted to generate a voltage responsive to the light generated by said illuminating device; whereby the voltage generated by said photosensitive element actuates said electronic switch circuit when the illuminating device is not lit.
Claim 11
Dependent Claim
28 words
The logic gate as recited in claim 6 including indicate means connected to said electronic switch circuit to provide visual indication when said electronic switch circuit is actuated.
Claim 12
Dependent Claim
99 words
The logic gate as recited in claim 8, wherein said buffer circuit includes: a master drive transistor connected between the gate output and a logic low voltage source, the control element of said master drive transistor being coupled to said gate input and said electronic switching circuit; and a slave drive transistor connected between the gate output and a logic high voLtage source, the control element of said slave drive transistor being coupled to said master drive transistor and said electronic switching circuit; wherein said electronic switch circuit turns off both the master and slave drive transistors when actuated.
Claim 13
Dependent Claim
100 words
The logic gate as recited in claim 7, wherein said electronic switch circuit is comprised of a first switching transistor and a second switching transistor and said electronic switching circuit is actuated when both switching transistors are actuated, and said current sensing circuit includes: a first input transistor connected to conduct current flowing into said gate input and connected to deactuate said first switching transistor in response to said conducted current; and a second input transistor connected to conduct current flowing out of said gate input and connected to deactuate said second switching transistor in response to said conducted current.
Claim 14
Dependent Claim
81 words
In a logic gate having a plurality of input terminals and an output terminal, the improvement comprising: switch means connected to said gate output terminal; and a plurality of fault sensing circuits, one connected to each gate input terminal to sense a malfunction condition at that terminal, and each one connected to said switch means to operate the switch means and to thereby open circuit said gate output terminal when a malfunction condition is sensed at its associated gate input terminal.
Claim 15
Dependent Claim
81 words
In a logic gate having a plurality of input terminals and an output terminal, the improvement comprising: switch means connected to said gate output terminal; and a plurality of fault sensing circuits, one connected to each gate input terminal to sense a malfunction condition at that terminal, and each one connected to said switch means to operate the switch means and to thereby open circuit said gate output terminal when a malfunction condition is sensed at its associated gate input terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-02 | 1977-01-01 | 1977-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-02 | 1981-01-01 | 1981-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-02 | 1985-01-01 | 1985-07-03 | $7700.00 | Window Closed / Lapsed |