Frequency divider

Claim 2

A divider circuit comprising, in combination: first and second two input logic gates, each of the type producing an output signal representing one binary value whenever the two input signals to that gate represent the same binary value and representing the other binary value whenever the two input signals to that gate represent different binary values; a common input signal terminal connected to one input terminal of both gates; a connection from the output terminal of the first gate to the other input terminal of the second gate; and a connection from the output terminal of the second gate to the other input terminal of the first gate.

Claim 3

The divider circuit recited in claim 1 wherein each of said first and second logic gates is an exclusive OR gate.

Claim 4

The divider circuit recited in claim 1 wherein each of said first and second logic gates is an exclusive NOR gate.

Claim 5

The divider circuit recited in claim 1 wherein each of said first and second logic gates includes a plurality of semiconductor devices, and said first logic gate changes state more rapidly than said second logic gate in response to a falling portion of the signal supplied to said common input signal terminal, and said second logic gate changes state more rapidly than said first logic gate in response to a rising portion of the signal supplied to said common input signal terminal.

Claim 6

The divider circuit recited in claim 1 wherein at least one of said logic gates includes inverter means at the output thereof.

Claim 7

The divider circuit recited in claim 1 wherein each of said logic gates includes first and second semiconductor devices of one conductivity type, each of said first and second semiconductor devices having a conduction path with a terminal at each end thereof and a gate electrode for controlling the conduction through said conduction path, said first and second semiconductor devices having a common connection at one terminal of the conduction paths thereof, reference source means, third and fourth semiconductor devices of the opposite conductivity type, each of said third and fourth semiconductor devices having a conduction path with a terminal at each end thereof and a gate electrode for controlling the conduction through said conduction path, said third and forth semiconductor devices having the conduction paths thereof connected in series between said common connection and said reference source means, the gate electrodes of said first and third semiconductor devices and one end of the conduction path of said second semiconductor device connected to said source means, and the gate electrodes of said second and fourth semiconductor devices and one end of the conduction path of said first semiconductor device connected to the output terminal of the other logic gate, said output terminal of each gate being connected to said common connection of the associated logic gate.

Claim 8

The divider circuit recited in claim 1 wherein each of said logic gates includes first semiconductor means, a conduction path with a terminal at each end thereof and a control electrode for controlling the conduction through said conduction path, said first semiconductor device having the conduction path thereof connected between said source means and said output terminal, reference source means, second and third semiconductor means each having a conduction path with a terminal at each end thereof and a control electrode for controlling the conduction through said conduction path, said second and third semiconductor devIces having the conduction paths thereof connected in series between said output terminal and said reference source means, the control electrodes of said first and second semiconductor means connected to the output terminal of the other logic gate, the control electrode of said third semiconductor means connected to said source means, said first semiconductor means being of one conductivity type, and said second and third semiconductor means being of another conductivity type.

Claim 9

The frequency divider recited in claim 6 including inverter means connected between said one terminal in one of said logic gates and the gate electrode of said second and fourth semiconductor devices of the other logic gate.

Claim 10

A divider circuit as set forth in claim 1 wherein each gate comprises a plurality of metal oxide semiconductor devices.

Claim 11

A divider circuit as set forth in claim 9 wherein each gate comprises complementary-symmetry, metal oxide semiconductor devices.