US3634658A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallel bit counter
Assignee: Unisys Corp
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Filing: 1970-03-19
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Granted: 1972-01-11
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Expires: 1990-03-19
Abstract
Abstract A counter that generates the binary coded sum of a number of equally weighted parallel input bits. The counter is constructed of a plurality of similar building block circuits and OR circuits; each building block circuit has first and second inputs and generates as first and second outputs the EXCLUSIVE OR function and the logical product, respectively, of the two inputs. Counters of 2n bits (where n is a positive integer equal to or greater than 2) may be constructed.
Inventors
- 👤 Richard R Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:56
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/607
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
255 words
A four-bit counter, comprising: first, second, third and fourth building block circuits each including: 1 and 2 inputs; 1 and 2 outputs; means intercoupling said 1 and 2 inputs and said 1 and 2 outputs for generating the EXCLUSIVE OR function of said 1 and 2 inputs at said 1 output and for generating the logical product of said 1 and 2 inputs at said 2 output; means coupling the EXCLUSIVE OR output of said first building block circuit to the 1 input of said third building block circuit; means coupling the EXCLUSIVE OR output of said first building block circuit to the 2 input of said third building block circuit; means coupling the logical product output of said first building block circuit to the 1 input of said fourth building block circuit; means coupling the logical product output of said second building block circuit to the 2 input of said fourth building block circuit; a logical OR circuit; means coupling the logical product output of said third building block circuit to a first input of said OR circuit; means coupling the EXCLUSIVE OR output of said fourth building block circuit to a second input of said OR circuit; the EXCLUSIVE OR output of said third building block circuit, the output of said OR circuit, and the logical product output of said fourth building block circuit generating 1, 2, 4 weighted counts, respectively, of the binary count of the number of significant bits coupled to the inputs of said first and second building block circuits.
Claim 2
Dependent Claim
255 words
A four-bit counter, comprising: first, second, third and fourth building block circuits each including: 1 and 2 inputs; 1 and 2 outputs; means intercoupling said 1 and 2 inputs and said 1 and 2 outputs for generating the EXCLUSIVE OR function of said 1 and 2 inputs at said 1 output and for generating the logical product of said 1 and 2 inputs at said 2 output; means coupling the EXCLUSIVE OR output of said first building block circuit to the 1 input of said third building block circuit; means coupling the EXCLUSIVE OR output of said first building block circuit to the 2 input of said third building block circuit; means coupling the logical product output of said first building block circuit to the 1 input of said fourth building block circuit; means coupling the logical product output of said second building block circuit to the 2 input of said fourth building block circuit; a logical OR circuit; means coupling the logical product output of said third building block circuit to a first input of said OR circuit; means coupling the EXCLUSIVE OR output of said fourth building block circuit to a second input of said OR circuit; the EXCLUSIVE OR output of said third building block circuit, the output of said OR circuit, and the logical product output of said fourth building block circuit generating 1, 2, 4 weighted counts, respectively, of the binary count of the number of significant bits coupled to the inputs of said first and second building block circuits.
Claim 3
Dependent Claim
251 words
An eight-bit counter, comprising: first, second and third building block circuits, each including: 1 and 2 inputs; 1 and 2 outputs; means intercoupling said 1 and 2 inputs and said 1 and 2 outputs for generating the EXCLUSIVE OR function of said 1 and 2 inputs at said 1 output and for generating the logical product of said 1 and 2 inputs at said 2 output; first and second four-bit counters defined by claim 2; means coupling the 1, 2, 4 weighted counts of said first four-bit counter to the 1 inputs of said first, second and third building block circuits, respectively; first and second logical OR circuits; means coupling the logical product output of said first building block circuit to a first input of said first OR circuit; means coupling the EXCLUSIVE OR output of said second building block circuit to a second input of said first OR circuit; means coupling the logical product output of said second building block circuit to a first input of said second OR circuit means coupling the EXCLUSIVE OR output of said third building block circuit to a second input of said second OR circuit; the EXCLUSIVE OR output of said first building block circuit, the outputs of said first and second OR circuit and the logical product output of said third building block circuit generating 1, 2, 4, 8 weighted counts, respectively, of the binary count of the number of significant bits coupled to the inputs of said first and second four-bit counters.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-10 | 1975-07-12 | 1976-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-10 | 1979-07-12 | 1980-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-10 | 1983-07-12 | 1984-01-11 | $7700.00 | Window Closed / Lapsed |