One transistor dynamic memory cell

Claim 2

A dynamic data storage system comprising in combination: a. a row and column matrix of dynamic storage cells, each cell being capable of storing binary data in the form of stored charge, respective cells including a single field-effect transistor, the gate of which is connected to a row enable line, the drain of which is connected to a column enable line and an extended portion of the source of which forms one plate of a capacitor coupling said source to circuit ground, the drains of all field-effect transistors of storage cells in a column being commonly connected and the gates of all FETs of storage cells in a row being commonly connected, a low resistivity region underlying the extended portion of the source to enhance capacitance between source and circuit ground; b. decoding means for randomly addressing selected cells; c. circuit means coupled to said decoding means for refreshing the charge stored in each cell of said matrix during each operating cycle; and d. input/output means for selectively writing information into and reading information from said matrix.

Claim 3

A dynamic data storage system as set forth in claim 1 wherein said decoding means includes a field-effect transistor connected in series with each column data input line, each transistor having a gate for selectively biasing on the column data line associated therewith.

Claim 4

A dynamic data storage system comprising in combination: a. a row and column matrix of dynamic storage cells, each cell being capable of storing binary data in the form of stored charge, respective cells including a single field-effect transistor, the gate of which is connected to a row enable line, the drain of which is connected to a column enable line and an extended portion of the source of which forms one plate of a capacitor coupling said source to circuit ground, the drains of all field-effect transistors of storage cells in a column being commonly connected and the gates of all FETs of storage cells in a row being commonly connected; b. decoding means for randOmly addressing selected cells; c. circuit means coupled to said decoding means for refreshing the charge stored in each cell of said matrix during each operating cycle; and d. input/output means for selectively writing information into and reading information from said matrix; and e. said refreshing circuit means comprises for each column data line: i. a first FET, one node of which is coupled to a voltage source and the gate of which is connected to first clocking means; ii. a second transistor connected in series with the other node of said first transistor, the second node of said second transistor being connected to circuit ground and the juncture of said first and second transistors being connected to said column data line; iii. a third transistor having one node connected to a voltage source and a gate electrode connected to a second clocking means; iv. a fourth field-effect transistor, the source and drain of which are connected in series between the other node of said third transistor and circuit ground and the gate of which is connected to said column data line, the juncture of said third and fourth transistors being connected to the gate of said second transistor; and v. a fifth FET, the source and drain of which are connected in parallel to the source and drain of said fourth transistor and the gate of which is connected to said first clocking means.

Claim 5

A dynamic data storage system comprising in combination: a. a row and column matrix of dynamic storage cells, each cell being capable of storing binary data in the form of stored charge, respective cells including a single field-effect transistor, the gate of which is connected to a row enable line, the drain of which is connected to a column enable line and an extended portion of the source of which forms one plate of a capacitor coupling said source to circuit ground, the drains of all field-effect transistors of storage cells in a column being commonly connected and the gates of all FETs of storage cells in a row being commonly connected; b. decoding means for randOmly addressing selected cells; c. circuit means coupled to said decoding means for refreshing the charge stored in each cell of said matrix during each operating cycle; and d. input/output means for selectively writing information into and reading information from said matrix; and e. said refreshing circuit means comprises for each column data line: i. a first FET, one node of which is coupled to a voltage source and the gate of which is connected to first clocking means; ii. a second transistor connected in series with the other node of said first transistor, the second node of said second transistor being connected to circuit ground and the juncture of said first and second transistors being connected to said column data line; iii. a third transistor having one node connected to a voltage source and a gate electrode connected to a second clocking means; iv. a fourth field-effect transistor, the source and drain of which are connected in series between the other node of said third transistor and circuit ground and the gate of which is connected to said column data line, the juncture of said third and fourth transistors being connected to the gate of said second transistor; and v. a fifth FET, the source and drain of which are connected in parallel to the source and drain of said fourth transistor and the gate of which is connected to said first clocking means.