Patent US3732440A successfully refreshed from Google Patents.
US3732440A
Expired / Lapsed
US
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Address decoder latch
Assignee: International Business Machines Corp
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Filing: 1971-12-23
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Granted: 1973-05-08
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Expires: 1991-12-23
Abstract
Abstract A dual condition latch circuit is disclosed which changes from an unlatched to a latched condition when a set input is applied only when a signal input from a logic gate is at a first level, and remains in the latched position after the signal input is removed. A first and second transistor with their emitters commonly connected to a current source and the collector of the first transistor connected to the base of the second transistor with a resistor connected between the collector of the first transistor and a reference point and the collector of the second transistor connected directly to the reference point constitutes the basic latching circuit. A set input pulse is applied to the base of the first transistor and a signal input level from a logic device is applied to the base of the second transistor such that only when the signal input is at a first level does the second transistor switch ''''on'''' when the set input pulses the first transistor from a conducting to a nonconducting state. If the signal input is not at a first level when the set input pulses the first transistor, the second transistor does not switch ''''on'''' and the circuit remains in an unlatched condition.
Inventors
- 👤 S Platt
- 👤 J Pomeranz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415; H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
246 words
A latch circuit requiring two conditional inputs to latch and remaining latched after the inputs are removed comprising: a first transistor having a first collector electrode, a first base electrode, and a first emitter electrode; a second transistor having a second collector electrode, a second base electrode connected to said first collector electrode and a second emitter electrode connected to said first emitter; a resistor connected between said first collector electrode and a first reference point, said first reference point also connected to said second collector electrode; a current source having a first electrode connected to a second reference point and a second electrode; a memory cell device connected between a first common point connected to said first and second emitter electrodes, and a second common point connected to said second electrode of said current source; a set input means connected to said first base electrode of said first transistor, wherein said set input means switches said first transistor from a conducting to a nonconducting state; a signal input means having a first output level and a second output level, connected to said second base electrode; wherein said second transistor goes from a nonconducting to a conducting state when said first output level is present and said first transistor goes from a conducting to a nonconducting state; and wherein said second transistor remains in a nonconducting state when said second output level is present and said first transistor goes from a conducting to a nonconducting state.
Claim 2
Dependent Claim
246 words
A latch circuit requiring two conditional inputs to latch and remaining latched after the inputs are removed comprising: a first transistor having a first collector electrode, a first base electrode, and a first emitter electrode; a second transistor having a second collector electrode, a second base electrode connected to said first collector electrode and a second emitter electrode connected to said first emitter; a resistor connected between said first collector electrode and a first reference point, said first reference point also connected to said second collector electrode; a current source having a first electrode connected to a second reference point and a second electrode; a memory cell device connected between a first common point connected to said first and second emitter electrodes, and a second common point connected to said second electrode of said current source; a set input means connected to said first base electrode of said first transistor, wherein said set input means switches said first transistor from a conducting to a nonconducting state; a signal input means having a first output level and a second output level, connected to said second base electrode; wherein said second transistor goes from a nonconducting to a conducting state when said first output level is present and said first transistor goes from a conducting to a nonconducting state; and wherein said second transistor remains in a nonconducting state when said second output level is present and said first transistor goes from a conducting to a nonconducting state.
Claim 3
Dependent Claim
32 words
The latch circuit of claim 1 wherein said memory cell device consists of a plurality of memory cell units connected in parallel between said first common point and said second common point.
Claim 4
Dependent Claim
97 words
The latch circuit of claim 1 wherein said signal input means is a third transistor having a third base electrode and a third collector electrode connected to said second base electrode, and a plurality of emitter regions each having an emitter electrode, and further comprising: a bilevel input means connected to each emitter electrode of said plurality of emitter regions having a first input level and a second input level wherein said third collector electrode is at said second output level when at least one emitter electrode in said third transistor is at said second input level.
Claim 5
Dependent Claim
39 words
The latch circuit of claim 3 further comprising: a reset input means connected to one of said emitter electrodes of said third transistor wherein said reset input means switches said third transistor from a nonconducting to a conducting state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-07 | 1976-11-06 | 1977-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-07 | 1980-11-06 | 1981-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-07 | 1984-11-06 | 1985-05-08 | $7700.00 | Window Closed / Lapsed |