Multi-channel analog multiplier and systems

Claim 2

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; holding means for receiving said products at said output terminals of the demultiplexing means; and compensating input means for applying reference signals to at least one pair of said input terminals, the product of which reference signals is a known value, that holding means associated with the product of such pair of reference signals being connected to said analog multiplier means for periodically adjusting the output thereof to said known value when said reference signals are applied as inputs thereto.

Claim 3

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; compensating input means for applying reference signals to at least one pair of said input terminals of the multiplexing means, the product of which reference signals is a known value, and means for periodically adjusting the output of said analog multiplier means to said known value when said reference signals are applied as inputs thereto.

Claim 4

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; compensating input means for applying reference signals to at least one pair of said input terminals of the multiplexing means, the product of which reference signals is a known value, and means for periodically adjusting the output of said analog multiplier means to said known value when said reference signals are applied as inputs thereto.

Claim 5

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; and clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; said analog multiplier means including an analog multiplier, scale factor amplifier means, and a compensating variable resistor connected between said analog multiplier and said scale factor amplifier means.

Claim 6

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; and clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; said analog multiplier means including an analog multiplier, scale factor amplifier means, and a compensating variable resistor connected between said analog multiplier and said scale factor amplifier means.

Claim 7

In a computational system as defined in claim 3 including compensating input means for applying reference signals to a pair of said input terminals of the analog multiplier means, the product of which reference signals is a known value, and means for varying said resistor to produce said known value at the output of said scale factor amplifier means when said reference signals are applied as inputs to said analog multiplier.

Claim 8

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; an external multiplier having the output of said clock means and the output at one terminal of said demultiplexing means as inputs thereto and having an output terminal; D.C. reference voltage means; said output terminal of the external multiplier and said D.C. reference voltage means being connected as one pair of inputs to said multiplexing means; a negative integrator connected to the output of said external multiplier and having an output terminal; the output terminal of said negative integrator and the output terminal of said demultiplexing means corresponding to said one pair of inputs to said multiplexing means being connected as another pair of inputs to said multiplexing means; and said another pair of inputs corresponding to said one terminal of the demultiplexing means, whereby the output of said external multiplier is a precisely modulated signal at the frequency of said clock means.

Claim 9

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; an external multiplier having the output of said clock means and the output at one terminal of said demultiplexing means as inputs thereto and having an output terminal; D.C. reference voltage means; said output terminal of the external multiplier and said D.C. reference voltage means being connected as one pair of inputs to said multiplexing means; a negative integrator connected to the output of said external multiplier and having an output terminal; the output terminal of said negative integrator and the output terminal of said demultiplexing means corresponding to said one pair of inputs to said multiplexing means being connected as another pair of inputs to said multiplexing means; and said another pair of inputs corresponding to said one terminal of the demultiplexing means, whereby the output of said external multiplier is a precisely modulated signal at the frequency of said clock means.

Claim 10

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; and means for operating on the output signal of at least one output terminal of said demultiplexing means to provide an output other than said product of the corresponding pair of input signals to said multiplexing means.

Claim 11

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; and means for operating on the output signal of at least one output terminal of said demultiplexing means to provide an output other than said product of the corresponding pair of input signals to said multiplexing means.

Claim 12

As a basic building block of a programmable analog computer, the combination of: at least one high accuracy analog multiPlier means; means for repetitively and successively applying input signal pairs as inputs to said multiplier means; means for separating the output products of said analog multiplier means into discrete product signal outputs corresponding to the input signal pairs; compensating means for periodically correcting the output of said analog multiplier means, said compensating means including means for applying a pair of reference signals, whose product is a fixed and known value, as an input signal pair to said multiplier means, and means connecting the corresponding product output signal to said multiplier means for causing its output to comply with said known value.

Claim 13

As a basic building block of a programmable analog computer, the combination of: at least one high accuracy analog multiPlier means; means for repetitively and successively applying input signal pairs as inputs to said multiplier means; means for separating the output products of said analog multiplier means into discrete product signal outputs corresponding to the input signal pairs; compensating means for periodically correcting the output of said analog multiplier means, said compensating means including means for applying a pair of reference signals, whose product is a fixed and known value, as an input signal pair to said multiplier means, and means connecting the corresponding product output signal to said multiplier means for causing its output to comply with said known value.

Claim 14

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; means for applying at least some input signal pairs to said multiplexing means which are modulated signals of a selected carrier frequency; and said clock means being slaved to said selected carrier frequency whereby the outputs of said demultiplexing means corresponding to said some input signal pairs are demodulated.

Claim 15

In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; means for applying at least some input signal pairs to said multiplexing means which are modulated signals of a selected carrier frequency; and said clock means being slaved to said selected carrier frequency whereby the outputs of said demultiplexing means corresponding to said some input signal pairs are demodulated.

Claim 16

In a computational system as defined in claim 8 including holding means at each of the outputs of said demultiplexing means.

Claim 17

In a computational system as defined in claim 9 including means operating on the outputs of at least one of said holding means for providing an output other than said product of the corresponding input signal pair.

Claim 18

In a computational system as defined in claim 8 including means operating on at least one of said products for producing an output other than said product.