System for computing in the hybrid domain

Claim 2

Hybrid computer apparatus having the capability of interfacing with external analog and digital data systems, receiving mode control signals, and performing the mathematical operations of addition, subtraction, multiplication and division, comprising: a. a digital register, for storing digital signals, having a plurality of binary stages; b. a current switch network, having a plurality of current switches, each connected to a respective one of said binary stages; c. a summing resistor network, having a plurality of binaryweighted resistors, each connected to a respective one of said current switches, and having an output terminal; d. at least one analog input resistor, connected to said output terminal; e. a comparator amplifier, connected to said output terminal; f. an operational amplifier, switchably connected to said output terminal; and, g. control means, for receiving said mode control signals and for controlling said apparatus to perform one of said mathematical operations according to the received mode control signal.

Claim 3

The apparatus described in claim 1 wherein said control means includes logic circuitry for controlling said apparatus to perform the mathematical operations of: a. multiplication and summation (D-A-S); b. summation and division (A-D-S); and c. multiplication and comparison (D-A-C), upon receiving a corresponding mode control signal.

Claim 4

The apparatus described in claim 1, having: a. first analog input means, for connecting an analog signal to each switch of said current switch network; b. analog output means, for connecting the output of said operational amplifier to an external analog device; c. a digital input network, for connecting a digital input signal to said digital register; and d. a digiTal output network, for reading out a digital signal stored in said digital register.

Claim 5

The apparatus described in claim 3, wherein is added a. programming means, connected to said hybrid computer apparatus, for providing said mode control signals; b. input multiplexer means, connected to and controlled by said programming means, for coupling at least one analog signal to said hybrid computer apparatus; and c. output distributor means, connected to and controlled by said programming means, for coupling said analog output means to one of a plurality of analog output channels, said programming means, input multiplexer means and output distributor means enabling said apparatus to be programmable and operate on a sequential-step basis.

Claim 6

The apparatus as described in claim 4, comprising: a. first switching means, for connecting said output terminal to said comparator amplifier, in which state said apparatus performs said division operation; b. second switching means, for connecting said output terminal to said operational amplifier, in which state said apparatus performs said multiplication operation; and c. compare operation logic means, connected to the output of said comparator amplifier, for providing a comparison output signal.

Claim 7

The apparatus as described in claim 4, wherein said programming means is comprised of electronic memory means being compatible with conventional electronic data processing input apparatus electronic register means coupled to said electronic memory means whereby the contents of any word contained in said memory means is decoded, logic programming means coupled to said electronic register means to generate logic signals for sequential control of said hybrid computing means, counter means and first address decoder means to sequentially step said programming means through its program, and second address decoder means to control said input multiplexer means and said output distributor means.

Claim 8

The invention as described in claim 4, wherein said programming means is comprised of an instruction patch board, operation decoder means to translate the instructions contained in said instruction patch board into corresponding electrical signals, timing sequencer means, coupled to and driven by said operation decoder means to generate control signals to control the operation of the hybrid computing means, instruction counter means and first patchboard address decoder means cooperating with said patch board to step the program contained in said instruction patch board sequentially, and second address decoder means to control said input multiplexer and said output distributor.

Claim 9

The invention as described in claim 7, wherein said timing sequencer means contains a plurality of operation timing sequencer units, each of said units containing secondary programming means whereby to step said programmable, sequential-step electronic computing system through a secondary program.

Claim 10

Hybrid computer apparatus, comprising: a. a common computing network, having a digital register, a current switch network connected to said digital register, and a summing resistor network connected to said current switch network, and having a plurality of binary-weighted resistors; b. an operational amplifier, switchably connected to the output of said summing resistor network; c. a comparator amplifier, switchably connected to the output of said summing resistor network; d. digital input means for connecting a digital input signal into said digital register; e. analog input means, for connecting an analog signal to said current switch network; f. said operational amplifier cooperating with said common computing network to provide digital to analog (DA) means for performing the operation of multiplication g. said comparator amplifier cooperating with said common computing network to provide analog to digital (AD) means for performing the operation of division; and, h. logic means for receiving proGram commands and controlling the operation of said DA means and said AD means.

Claim 11

Hybrid computer apparatus, comprising: a. a common computing network, having a digital register, a current switch network connected to said digital register, and a summing resistor network connected to said current switch network, and having a plurality of binary-weighted resistors; b. an operational amplifier, switchably connected to the output of said summing resistor network; c. a comparator amplifier, switchably connected to the output of said summing resistor network; d. digital input means for connecting a digital input signal into said digital register; e. analog input means, for connecting an analog signal to said current switch network; f. said operational amplifier cooperating with said common computing network to provide digital to analog (DA) means for performing the operation of multiplication g. said comparator amplifier cooperating with said common computing network to provide analog to digital (AD) means for performing the operation of division; and, h. logic means for receiving proGram commands and controlling the operation of said DA means and said AD means.

Claim 12

The apparatus described in claim 9, wherein is added: a. programming means, connected to said hybrid computer apparatus, for providing said program commands; b. input multiplexer means, connected to and controlled by said programming means, for coupling at least one analog signal to said hybrid computer apparatus; and c. output distributor means, connected to and controlled by said programming means, for coupling said analog output means to one of a plurality of analog output channels, said programming means, input multiplexer means and output distributor means enabling said apparatus to be programmable and operate on a sequential-step basis.

Claim 13

Hybrid computing means, capable of receiving analog data signals, digital data signals, reference signals, and mode control signals, and capable of providing analog data output signals and digital data output signals, comprising: a. a comparator amplifier; b. an operational amplifier; c. a summing resistor network, having a common summing junction; d. a current switch network, coupled to said summing resistor network; e. a digital register, coupled to said summing resistor network through said current switch network; f. control circuitry, coupled to and driving said digital register; g. a plurality of analog input resistors; and h. switching means, comprising, i. first switching means, to couple the input of said comparator amplifier to said common summing junction, the output of said comparator amplifier to said control circuitry, an analog data signal to one of said analog input resistors, and a reference signal to said current switch network, whereby to place said hybrid computing element in the A-D mode; ii. second switching means, to couple the input of said comparator amplifier to said common summing junction, the output of said comparator amplifier to said control circuitry, a plurality of analog data signals to said analog input resistors, and a reference signal to said current switch network, whereby to place said hybrid computing element in the A-D-S mode; iii. third switching means, to couple the input of said operational amplifier to said common summing junction, a digital data signal to said digital register, and a reference signal to said current switch network, whereby to place said hybrid computing element in the D-A mode; iiii. fourth switching means, to couple the input of said operational amplifier to said common summing junction, an analog data signal to one of said analog input resistors, a digital input signal to said digital register, and a reference signal to said current switch network, whereby to place said hybrid computing element in the D-A-S mode; iiiii. fifth switching means, to couple the input of said comparator amplifier to said common summing junction, the output of said comparator amplifier to an output terminal, a digital input signal to said digital register, a reference signal to said current switch network, and an analog signal to one of said input resistors, whereby to place said hybrid computing element in the D-A-C mode; iiiiii. sixth switching means, to couple the input of said operational amplifier to said common summing junction, and a plurality of analog data signals to said analog input resistors, whereby to place said hybrid computing element in the A/S mode.

Claim 14

Hybrid computing means, capable of receiving analog data signals, digital data signals, reference signals, and mode control signals, and capable of providing analog data output signals and digital data output signals, comprising: a. a comparator amplifier; b. an operational amplifier; c. a summing resistor network, having a common summing junction; d. a current switch network, coupled to said summing resistor network; e. a digital register, coupled to said summing resistor network through said current switch network; f. control circuitry, coupled to and driving said digital register; g. a plurality of analog input resistors; and h. switching means, comprising, i. first switching means, to couple the input of said comparator amplifier to said common summing junction, the output of said comparator amplifier to said control circuitry, an analog data signal to one of said analog input resistors, and a reference signal to said current switch network, whereby to place said hybrid computing element in the A-D mode; ii. second switching means, to couple the input of said comparator amplifier to said common summing junction, the output of said comparator amplifier to said control circuitry, a plurality of analog data signals to said analog input resistors, and a reference signal to said current switch network, whereby to place said hybrid computing element in the A-D-S mode; iii. third switching means, to couple the input of said operational amplifier to said common summing junction, a digital data signal to said digital register, and a reference signal to said current switch network, whereby to place said hybrid computing element in the D-A mode; iiii. fourth switching means, to couple the input of said operational amplifier to said common summing junction, an analog data signal to one of said analog input resistors, a digital input signal to said digital register, and a reference signal to said current switch network, whereby to place said hybrid computing element in the D-A-S mode; iiiii. fifth switching means, to couple the input of said comparator amplifier to said common summing junction, the output of said comparator amplifier to an output terminal, a digital input signal to said digital register, a reference signal to said current switch network, and an analog signal to one of said input resistors, whereby to place said hybrid computing element in the D-A-C mode; iiiiii. sixth switching means, to couple the input of said operational amplifier to said common summing junction, and a plurality of analog data signals to said analog input resistors, whereby to place said hybrid computing element in the A/S mode.