Analog-digital computer interconnection system

Claim 2

Hybrid analog-digital computer apparatus connected to be operable in conjunction with a digital computer, comprising, in combination: first register means connected to be addressed by said digital computer to provide first and second signals; and input-output bus comprising a plurality of lines connected to data input and output lines of said digital computer; second register means; firs gating circuit means operable in response to said first signal to connect said input-output bus to said second register means; first decoder means operable to decode the contents of said second register means to provide an operation code signal on one or more of a plurality of lines to specify one or more operations to be performed within said hybrid computer apparatus; third register means; second gating circuit means responsive to said second signal, to an enabling signal from said digital computer and to selected ones of said operation code signals and operative to connect a plurality of stages of said third register means to said input-output bus; and further computer apparatus including a plurality of analog computer elements connected to be addressed by and have their operating modes controlled by the contents of said third register means.

Claim 3

Apparatus according to claim 1 having a plurality of manual controls encoder means responsive to operation of said manual controls for applying signals via said second gating circuit to said third register means; and third gating circuit means responsive to occurrence of said first signal or certain of said operation code signals for providing an inhibiting signal to prevent the operation of said manual controls from altering the contents of said third register means.

Claim 4

Apparatus according to claim 1 in which said analog computer elements include a plurality of digital-to-analog converters; third gating circuit means responsive to one of said operation code signals, said second signal, and to said enabling signal; and fourth gating circuit means responsive to the contents of a portion of said third register means, said third and fourth gating circuit means being operable to connect said input-output bus to a selected one of said digital-to-analog converters in accordance with said contents of said portion of said third register means.

Claim 5

Apparatus according to claim 1 in which said analog computer elements include a plurality of servo-positioned potentiometers; digital code conversion means; digital-to-analog converter means operative to convert the output of said code conversion means to an analog signal; third gating circuit means responsive to one of said operation code signals, to said second signal, and to said enabling signal, and operative to connect said input-output bus to said digital code conversion means; and selective switching means responsive to the contents of a portion of said third register means for connecting said analog signal to adjust a selected one of said potentiometers in accordance with said contents of said portion of said third register means.

Claim 6

Apparatus according to claim 1 in which said analog computer elements include an analog-to-digital converter means; third gating circuit means responsive to one of said operation code signals, to said second signal, and to said enabling signal, and operative to connect the output of said analog-to-digital converter means to said input-output bus; selective switching means for connecting a selected analog signal as an input to said analog-to-digital converter means; and means responsive to the contents of a portion of said third register means for controlling said selective switching means.

Claim 7

Apparatus according to claim 1 in which said further computer apparatus includes an analog-to-digital converter operative to convert analog signals from a plurality of said analog computer elements to digital signals and operative to provide a control signal while said converter is converting a given one of said analog signals; and third gating circuit means responsive to one of said operation code signals and to said control signal to prevent the application of said enabling signal to said second gating circuit means while said converter is converting one of said analog signals.

Claim 8

Apparatus according to claim 1 having switching means operable in response to one of said operation code signals to reconnect a portion of said third register means into a counter circuit configuration; and third gating circuit means responsive to said one of said operation code signals and to said second signal and operative to apply an incrementing pulse to advance the count in said portion of said third register means.

Claim 9

Apparatus according to claim 1 in which said analog computer elements include a plurality of analog electronic integrators, and in which said apparatus includes switching means responsive to the contents of a portion of said third register means and operable to connect said integrators to operate with a selected time scale, and to switch between operating, resetting and holding modes in accordance with said contents of said portion of said third register means.

Claim 10

Apparatus according to claim 1 in which said further computer apparatus includes a patchboard having groups of patchholes; a plurality of control-line registers, third gating circuit means for connecting the contents of each of said control-line registers to a respective group of said patchholes; fourth gating means responsive to one of said operation code signals, to said second signal and to said enabling signal and operative to connect said input-output bus to a selected one of said control-line registers; and fifth gating circuit means responsive to said one of said operation code signals and to said second signal and operable to apply an inhibiting signal to said third gating circuit means to prevent the signals at said group of patchholes from changing during the duration of said second signal.

Claim 11

Apparatus according to claim 1 in which said further computer apparatus includes a patchboard having groups of patchholes; a plurality of sense-line registers; third gating circuit means for connecting each group of said patchholes to a respective one of said sense-line registers; fourth gating circuit means responsive to one of said operation code signals, to said second signal and to said enabling signal, and operative to connect the contents of a selected one of said sense-line registers to said input-output bus; and fifth gating circuit means responsive to said one of said operation code signals and to said second signal and operable to apply an inhibiting signal to said third gating circuit means, to prevent the signals at said group of patchholes from changing the contents of said selected one of said sense-line registers during the duration of said second signal.

Claim 12

AppaRatus according to claim 1 having a third gating circuit responsive to a fourth signal and in which said input-output bus is connected to said data input and output lines of said digital computer through said third gating circuit, said further computer apparatus including a patchboard having a patchhole to which logic signals may be selectively patched; and circuit means for connecting said patchhole to provide said fourth signal to said third gating circuit to disconnect said input-output bus from the input and output lines of said digital computer.

Claim 13

Apparatus according to claim 1 in which said second gating circuit means is operative in response to said second signal, a first one of said operation code signals and to a first enabling signal from said digital computer to apply data signals from said digital computer over said input-output bus to write said data signals in a plurality of stages of said third register means, and in which said second gating circuit means is operative to response to said second signal, a second one of said operation code signals and to a second enabling signal from said digital computer to read out the contents of a plurality of stages of said third register means over said input-output bus to said digital computer.

Claim 14

Apparatus according to claim 1 in which said further computer apparatus includes a plurality of synchronous logic circuits timed by a clock pulse source; a plurality of interrupt register stages; a patchboard having a plurality of patchholes; and third gating circuit means operative in the absence of said enabling signal, curing one level of said timing pulses from said clock pulse source, and in the absence of a selected one of said operation code signals for connecting said patchholes to respective ones of said interrupt register stages.

Claim 15

Apparatus according to claim 1 in which said third register means has a greater bit capacity than the number of lines of said input-output bus; third gating circuit means responsive to said selected ones of said operation code signals and to said enabling signals for providing a timed signal, said timed signal being connected to said second gating circuit means to cause said input-output bus to be connected successively to first and second portions of said third register means.

Claim 16

Apparatus according to claim 1 in which said further computer apparatus includes patchboard means having a plurality of patchholes; a plurality of sense-line registers; third gating circuit means for connecting a respective group of said patchholes to each of said sense-line registers; fourth gating circuit means responsive to a first one of said operation code signals, to said second signal and to a first enabling signal from said digital computer and operative to connect the contents of a selected one of said sense-line registers to said input-output bus; a temporary storage register; 50 gating circuit means operative to connect signals on said input-output bus into said temporary storage register; sixth gating circuit means operative to connect data stored in said temporary storage register to said input-output bus; a plurality of control-line registers; seventh gating circuit means for connecting a respective group of said patchholes to each of said control line registers; eighth gating circuit means responsive to a second one of said operation code signals, to said second signal and to a second enabling signal from said digital computer and operative to connect the signal on said input-output bus to a selected one of said control-line registers; means for deriving a first data transfer signal in synchronism with said first one of said operation code signals, a first occurrence of said second signal and a first occurrence of said first enabling signal to enable said fifth gating circuit means to transfer the contents of said selected one of said sense-line registers via said input-output bus into said temporary storage register, and for deriving a succeeding second data transfer signal iN synchronism with said second one of said operation code signals, a second occurrence of said second signal and said second enabling signal to enable said sixth gating circuit means to transfer the contents of said temporary storage register via said input-output bus to said selected one of said control-line registers.

Claim 17

Apparatus according to claim 3 in which each of said digital-to-analog converters includes an initial register means and a final register means and fifth gating circuit means operable in response to a second of said operation code signals and said first signal to connect the contents of each of the initial register means, said third and fourth gating circuit means being operable to connect said input-output bus to the initial register means of said selected one of said digital-to-analog converters, and each of said digital-to-analog converters being operable to convert the contents of its respective final register means to provide a respective analog signal.

Claim 18

Apparatus according to claim 5 having fourth gating circuit means responsive to said operation code signal to control said selective switching means to advance sequentially to connect a series of analog signals in a predetermined sequence to said analog-to-digital converter means upon the occurrence of successive ones of said second signals, irrespective of the contents of said portion of said third register means.

Claim 19

Apparatus according to claim 5 having fourth gating circuit means responsive to said first and second signals and to said one of said operation code signals for applying a control pulse to said analog-to-digital converter means to initiate conversion of said selected analog signal by said analog-to-digital converter means.

Claim 20

Apparatus according to claim 13 having fourth gating means connected to said plurality of interrupt register stages and enabled by the opposite level of said timing pulses for applying an output signal to said digital computer whenever one or more of said stages have been set by the signals applied to their respective patchholes.

Claim 21

Apparatus according to claim 13 in which said plurality of interrupt register stages are AC-coupled via said third gating circuit means to said patchholes; and means including a fourth gating circuit and time-delay means responsive to said selected one of said operation code signals and said enabling signal for applying a signal to reset said stages to a reference condition a predetermined time after said stages have been connected to said input-output bus.

Claim 22

Apparatus according to claim 3 having a fourth register means; sixth gating circuit means responsive to a selected one of said operation code signals and to the contents of a portion of said third register means and operable to connect a plurality of the lines of said input-output bus to said fourth register means; and further gating circuit means responsive to the contents of said fourth register means for applying a signal to enable said fifth gating circuit means irrespective of the presence or absence of said second operation code signal and said second signal.

Claim 23

Apparatus according to claim 13 having fourth gating circuit means responsive to said selected one of said operation code signals and said enabling signal for connecting the contents of said register stages to said input-output bus.