Patent US3629610A successfully refreshed from Google Patents.
US3629610A
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Ecl logic circuit
Assignee: Siemens AG
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Filing: 1970-03-09
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Granted: 1971-12-21
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Expires: 1990-03-09
Abstract
Abstract An emitter-coupled logic circuit for realization of an AND linkage in positive logic, utilizing a differential amplifier in the form of emitter-coupled transistors, in which a polyemitter transistor forms the control input for the differential amplifier and has the emitter electrodes thereof connected over respective emitter-follower stages to the respective input signal sources.
Inventors
- 👤 Wilhelm Wilhelm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:25
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0863
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
96 words
An emitter-coupled logic circuit for realization of an AND linkage in positive logic, comprising a differential amplifier in the form of emitter-coupled transistors, the base of one of which forms an input circuit therefor and which is to be operatively connected to a plurality of input signal sources, a polyemitter transistor having its base and collector tied together and connected to said base of said emitter-coupled transistors, and an emitter follower stage for each of said input signal sources, operatively connected thereto, and having its emitter connected to a selected emitter diode of said polyemitter transistor.
Claim 2
Dependent Claim
96 words
An emitter-coupled logic circuit for realization of an AND linkage in positive logic, comprising a differential amplifier in the form of emitter-coupled transistors, the base of one of which forms an input circuit therefor and which is to be operatively connected to a plurality of input signal sources, a polyemitter transistor having its base and collector tied together and connected to said base of said emitter-coupled transistors, and an emitter follower stage for each of said input signal sources, operatively connected thereto, and having its emitter connected to a selected emitter diode of said polyemitter transistor.
Claim 3
Dependent Claim
67 words
An emitter-coupled logic circuit according to claim 1, wherein the respective emitter-follower emitter diode paths for said polyemitter transistor are provided with biasing resistors which individually have a value such that in the presence of an input signal equal to a predetermined auxiliary voltage at the differential Amplifier, the associated follower emitter current and the current of the corresponding emitter diode of the polyemitter transistor are equal.
Claim 4
Dependent Claim
53 words
An emitter-coupled logic circuit according to claim (1 or) 2, wherein each transistor of the differential amplifier has its collector operatively connected to an output over a respective emitter follower stage, one of which provides output signals in a normal position, and the other of which provides output signals in an inverted position.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-20 | 1975-06-21 | 1975-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-20 | 1979-06-21 | 1979-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-20 | 1983-06-21 | 1983-12-21 | $7700.00 | Window Closed / Lapsed |