Electronic comparator circuit

Claim 1

A noise-rejecting electronic analogue comparator system adapted to provide an output logic signal which swings without appreciable time delay from one to the other of two levels whenever the sum of applied input signals changes sign, but adapted not to respond to signals having less than a predetermined time duration, comprising, in combination: an electronic comparator having input circuit means connected to receive said input signals and to provide first and second mutually opposite logic signals which swing substantially immediately from one state to an opposite state upon a change in the sign of said sum of said input signals; first and second unidirectional delay circuit means, each responsive to a respective one of said first and second logic signals, each operative to provide a respective output logic signal transition in one direction substantially immediately upon transition of its respective logic input signal from one state to a second state, and each operative to provide a respective output logic signal transition in an opposite direction only after its respective input logic signal has remained in its first state for a predetermined time period; and bistable circuit means having a pair of mutually oppositely-effective input lines connected to receive the output signals from said First and second delay circuit means and to provide said output logic signal, said input circuit means of said electronic comparator having a lead timeconstant commensurate with said predetermined time period.