Gated symmetrical five layer switch with shorted emitters

Claim 1

A GATED SEMICONDUCTOR SWITCHING DEVICE COMPRISING A SEMICONDUCTOR BODY HAVING: A FIRST N-TYPE SEMICONDUCTOR REGION; SUBSTANTIALLY COEXTENSIVE FIRST AND SECOND P-TYPE SEMICONDUCTOR REGIONS ON EACH SIDE OF THE FIRST N-TYPE SEMICONDUCTOR REGION FORMING JUNCTIONS THEREWITH; SECOND AND THIRD N-TYPE SEMICONDUCTOR REGIONS ADJACENT THE FIRST AND SECOND P-TYPE SEMICONDUCTOR REGIONS, RESPECTIVELY, FORMING FIRST AND SECOND EMITTERBASE JUNCTION AREAS OVER PORTIONS OF THE RESPECTIVE FIRST AND SECOND P-TYPE SEMICONDUCTOR REGIONS WHICH ARE NOT COEXTENSIVE LEAVING EXPOSED PORTIONS OF THE RESPECTIVE P-TYPE SEMICONDUCTOR REGIONS; TWO N-REGION TERMINAL MEANS, ONE CONNECTED TO THE SECOND AND ONE CONNECTED TO THE THIRD N-TYPE SEMICONDUCTOR REGIONS; TWO P-REGION TERMINAL MEANS, ONE CONNECTED TO THE FIRST AND ONE CONNECTED TO THE SECOND P-TYPE SEMICONDUCTOR REGIONS. TWO CONDUCTOR MEANS SUCH CONNECTING AN N-REGION TERMINAL TO ITS ADJACENT P-REGION TERMINAL, AND