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US3356858A Expired / Lapsed US ⏱️ 0.0 years remaining

Low stand-by power complementary field effect circuitry

Assignee: Fairchild Semiconductor Corp
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Filing: 1963-06-18
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Granted: 1967-12-05
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Expires: 1983-06-18
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Abstract

No abstract record available.

Inventors

  • 👤 Frank M Wanlass

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 16:05
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858; H10D99/00

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 293 words
A CIRCUIT COMPRISING A FIRST INSULATED GATE FIELD-EFFECT TRANSISTOR HAVING A SUBSTRATE OF ONE CONDUCTIVITY TYPE, AN INSULATING LAYER ADJACENT SAID SUBSTRATE, A METAL LAYER UPON SAID INSULATING LAYER OPPOSITE SAID SUBSTRATE, AND A CHANNEL REGION ADJACENT SAID INSULATING LAYER HAVING A CONDUCTIVITY TYPE OPPOSITE SAID SUBSTRATE UPON APPLICATION OF A FIRST PREDETERMINED BIAS VOLTAGE TO SAID METAL LAYER, THEREBY FORMING A PN JUNCTION BETWEEN SAID SUBSTRATE AND SAID CHANNEL REGION, SOURCE AND DRAIN ELECTRODES ON OPPOSITE ENDS OF SAID CHANNEL REGION, A SECOND INSULATED GATE FIELDEFFECT TRANSISTOR HAVING A SUBSTRATE OF SAID OPPOSITE CONDUCTIVITY TYPE, AN INSULATING LAYER ADJACENT SAID SUBSTRATE, A METAL LAYER UPON SAID INSULATING LAYER OPPOSITE SAID SUBSTRATE, AND A CHANNEL REGION ADJACENT SAID INSULATING LAYER HAVING SAID ONE CONDUCTIVITY TYPE UPON APPLICATION OF A SECOND PREDETERMINED BIAS VOLTAGE TO SAID METAL LAYER OF POLARITY OPPOSITE TO SAID FIRST PREDETERMINED BIAS VOLTAGE, SOURCE AND DRAIN ELECTRODES ON OPPOSITE ENDS OF SAID CHANNEL REGION, ONE OF SAID SOURCE AND DRAIN ELECTRODES OF SAID FIRST INSULATED GATE FIELD-EFFECT TRANSISTOR BEING COUPLED TO ONE OF SAID SOURCE AND DRAIN ELECTRODES OF SAID SECOND INSULATED FIELD-EFFECT TRANSISTOR, A MEANS FOR APPLYING A FIXED BIAS VOLTAGE ACROSS THE OTHER OF SAID SOURCE AND DRAIN ELECTRODES OF SAID FIRST AND SECOND INSULATED FIELD-EFFECT TRANSISTORS, AND A MEANS FOR APPLYING A VOLTAGE SIGNAL OF A SINGLE PREDETERMINED POLARITY TO BOTH OF SAID METAL LAYERS OF SAID FIRST AND SECOND INSULATED GATE FIELD-EFFECT TRANSISTORS ADAPTED TO RENDER SAID FIRST INSULATED GATE FIELD-EFFECT TRANSSISTOR CONDUCTIVE BETWEEN ITS SOURCE AND DRAIN ELECTRODES WHILE RENDERING SAID SECOND INSULATED GATE FIELD-EFFECT TRANSISTOR NON-CONDUCTIVE BETWEEN ITS SOURCE AND DRAIN ELECTRODES, WHEREBY SAID SECOND NON-CONDUCTIVE INSULATED GATE FIELD-EFFECT TRANSISTOR IS EMPLOYED AS THE ACTIVE LOAD FOR SAID FIRST CONDUCTIVE INSULATED GATE FIELD-EFFECT TRANSISTOR.

References Cited (Backward Citations)

US3222610A Cited
US3215861A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1970-12-04 1971-06-05 1971-12-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1974-12-04 1975-06-05 1975-12-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1978-12-04 1979-06-05 1979-12-05 $7700.00 Window Closed / Lapsed

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