Parity check gate circuit employing transistor driven beyond saturation

Claim 1

A PARITY CHECK GATE CIRCUIT COMPRISING: A FIRST TRANSISTOR HAVING A BASE, AN EMITTER ELECTRODE AND A COLLECTOR ELECTRODE; A Y RESISTANCE NETWORK HAVING TWO LEGS OF EQUAL IMPEDANCE EACH ARRANGED TO RECEIVE AN INPUT SIGNAL AND THE THIRD LEG COUPLED TO A RELATIVELY POSITIVE BIAS VOLTAGE SOURCE; MEANS COUPLING THE BASE OF SAID FIRST TRANSISTOR TO THE JUNCTION OF SAID Y-NETWORK; IMPEDANCE MEANS COUPLING THE COLLECTOR ELECTRODE TO THE RELATIVELY POSITIVE BIAS VOLTAGE SOURCE; IMPEDANCE MEANS COUPLING THE EMITTER ELECTRODE TO A RELATIVELY NEGATIVE VOLTAGE SOURCE, SAID IMPEDANCE MEANS, THE BIAS VOLTAGE AND THE INPUT SIGNALS ON SAID NETWORK BEING SELECTED SO THAT WHEN BOTH INPUT SIGNALS ARE MOST POSITIVE, SAID FIRST TRANSISTOR IS DRIVEN BEYOND SATURATION WHEREBY THE COLLECTOR ELECTRODE IS POSITIVE AS A FUNCTION OF THE INPUT SIGNALS, AND WHEN ONE IS MOST POSITIVE AND THE OTHER NEGATIVE, SAID FIRST TRANSISTOR IS "ON," WHEREBY THE COLLECTOR ELECTRODE IS NEGATIVE; A NEGATIVE CLAMPING MEANS COUPLED TO THE EMITTER ELECTRODE TO LIMIT THE NEGATIVE EXCURSION THEREOF TO LESS THAN THE NEGATIVE EXCURSION OF THE JUNCTION WHEREBY BOTH INPUT SIGNALS GOING NEGATIVE WILL TURN OFF SAID FIRST TRANSISTOR; AN OUTPUT TERMINAL COUPLED BY IMPEDANCE MEANS TO THE RELATIVELY NEGATIVE VOLTAGE SOURCE TO PROVIDE AN OUTPUT SIGNAL CORRESPONDING TO THE NEGATIVE INPUT SIGNAL MAGNITUDE; A SECOND TRANSISTOR COUPLED TO GROUND SAID OUTPUT TERMINAL AND THUS PROVIDE A MOST POSITIVE OUTPUT SIGNAL CORRESPONDING TO A MOST POSITIVE INPUT SIGNAL MAGNITUDE; AND MEANS COUPLING SAID SECOND TRANSISTOR TO BE CONDUCTIVE ONLY WHEN THE COLLECTOR ELECTRODE OF SAID FIRST TRANSISTOR IS NEGATIVE.