skerritt

Claim 1

AN "EXCLUSIVE OR" LOGICAL CIRCUIT COMPRISING FIRST AND SECOND TRANSISTORS HAVING BASE, COLLECTOR AND EMITTER ELEMENTS, SAID FIRST TRANSISTOR BEING CONNECTED IN GROUNDED EMITTER CONFIGURATION, SAID SECOND TRANSISTOR BEING CONNECTED IN EMITTER FOLLOWER CONFIGURATION, SAID TRANSISTORS HAVING AN INPUT AND AN OUTPUT CIRCUIT, SAID INPUT CIRCUIT INCLUDING FIRST AND SECOND INPUT TERMINALS FOR APPLYING FIRST AND SECOND INPUT SIGNALS TO SAID LOGICAL CIRCUIT, COINCIDENCE CIRCUIT MEANS INTERCONNECTED BETWEEN SAID INPUT TERMINALS AND THE BASE OF SAID FIRST TRANSISTOR, MEANS INTERCONNECTED BETWEEN SAID INPUT TERMINALS AND THE COLLECTOR OF SAID SECOND TRANSISTOR, MEANS CONNECTING THE COLLECTOR OF SAID FIRST TRANSISTOR TO THE BASE OF SAID SECOND TRANSISTOR, SAID LAST-MENTIONED MEANS INCLUDING MEANS FOR BIASING SAID SECOND TRANSISTOR INTO THE ACTIVE REGION OF OPERATION IN RESPONSE TO THE CONDUCTION OF SAID FIRST TRANSISTOR, AND INTO THE SATURATION REGION OF OPERATION IN RESPONSE TO THE CUT OFF OF CONDUCTION OF SAID FIRST TRANSISTOR AND MEANS COUPLING THE EMITTER OF SAID SECOND TRANSISTOR TO SAID OUTPUT CIRCUIT WHEREBY AN OUTPUT SIGNAL IS PROVIDED HAVING A SIGNAL LEVEL APPROACHING THE LEVEL OF THE BASE OF SAID SECOND TRANSISTOR WHEN SAID SECOND TRANSISTOR IS IN SAID ACTIVE REGION, AND HAVING A SIGNAL LEVEL APPROACHING THE SIGNAL LEVEL OF THE COLLECTOR OF SAID SECOND TRANSISTOR WHEN SAID SECOND TRANSISTOR IS IN SAID SATURATION REGION.