US20160140039A1 — Providing multiple memory modes for a processor i…

Claim 1

Independent Claim 77 words

1 . A processor comprising: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, wherein the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory.

Claim 2

Dependent Claim 77 words

1 . A processor comprising: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, wherein the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory.

Claim 3

Dependent Claim 58 words

2 . The processor of claim 1 , wherein a first distance indication is to be associated with the in-package memory and a second distance indication is to be associated with the platform memory, wherein the second distance indication is to indicate that the platform memory is closer to the at least one core than the in-package memory.

Claim 4

Dependent Claim 71 words

3 . The processor of claim 2 , further comprising: a first node including the at least one core and a first portion of the platform memory; a second node including at least one other core formed on the die and a second portion of the platform memory; a third node including a first portion of the in-package memory; and a fourth node including a second portion of the in-package memory.

Claim 5

Dependent Claim 53 words

4 . The processor of claim 3 , wherein the at least one core is to link to the first portion of the platform memory with the second distance indication, and the at least one other core is to link to the first portion of the in-package memory with the first distance indication.

Claim 6

Dependent Claim 35 words

5 . The processor of claim 1 , further comprising a first storage to store a first table having a plurality of entries to identify bandwidth associated with the in-package memory and the platform memory.

Claim 7

Dependent Claim 36 words

6 . The processor of claim 5 , wherein a bandwidth between the at least one core and the in-package memory is greater than a bandwidth between the at least one core and the platform memory.

Claim 8

Dependent Claim 35 words

7 . The processor of claim 1 , wherein the in-package memory and the platform memory are to share a common address space, the in-package memory and the platform memory comprising a non-uniform memory architecture.

Claim 9

Dependent Claim 48 words

8 . The processor of claim 1 , further comprising: a first system address decoder to associate a first portion of a common address space with the platform memory; and a second address decoder to associate a second portion of the common address space with the in-package memory.

Claim 10

Dependent Claim 53 words

9 . The processor of claim 8 , wherein the second memory controller is to enable at least a portion of an operating system (OS) to be stored in the platform memory and the first memory controller is to enable user defined information of an application to be stored in the in-package memory.

Claim 11

Dependent Claim 158 words

10 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising: identifying a first node including one or more cores of a processor package and at least a portion of a platform memory coupled to the processor package and associating a first distance between the one or more cores and the at least portion of the platform memory; and identifying a second node including at least a portion of an in-package memory of the processor package and associating a second distance between the one or more cores and the at least portion of the in-package memory, wherein the second distance is greater than the first distance, the one or more cores and the in-package memory internal to the processor package and the at least portion of the platform memory external to the processor package.

Claim 12

Dependent Claim 158 words

10 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising: identifying a first node including one or more cores of a processor package and at least a portion of a platform memory coupled to the processor package and associating a first distance between the one or more cores and the at least portion of the platform memory; and identifying a second node including at least a portion of an in-package memory of the processor package and associating a second distance between the one or more cores and the at least portion of the in-package memory, wherein the second distance is greater than the first distance, the one or more cores and the in-package memory internal to the processor package and the at least portion of the platform memory external to the processor package.

Claim 13

Dependent Claim 30 words

11 . The machine-readable medium of claim 10 , wherein the method further comprises populating one or more configuration tables with information regarding the platform memory and the in-package memory.

Claim 14

Dependent Claim 36 words

12 . The machine-readable medium of claim 11 , wherein the one or more configuration tables comprises a platform memory topology table (PMTT), the PMTT including bandwidth information for the platform memory and the in-package memory.

Claim 15

Dependent Claim 30 words

13 . The machine-readable medium of claim 12 , wherein the method further comprises generating a bandwidth file based at least in part on the bandwidth information in the PMTT.

Claim 16

Dependent Claim 45 words

14 . The machine-readable medium of claim 10 , wherein the method further comprises setting the at least portion of the platform memory to a base address of a single address space including the at least portion of the platform memory and the in-package memory.

Claim 17

Dependent Claim 57 words

15 . The machine-readable medium of claim 10 , wherein the method further comprises: receiving a first memory allocation request and allocating a range within the at least portion of the platform memory responsive thereto; and receiving a second memory allocation request and allocating a range within the at least portion of the in-package memory responsive thereto.

Claim 18

Dependent Claim 93 words

16 . The machine-readable medium of claim 10 , wherein the method further comprises: in a first memory mode, maintaining the in-package memory to be a cache memory for the platform memory; in a second memory mode, providing a single address space formed of the platform memory and the in-package memory; and in a third memory mode, maintaining a first portion of the in-package memory to be the cache memory for the platform memory, and maintaining a second portion of the in-package memory to form the single address space with the platform memory.

Claim 19

Dependent Claim 132 words

17 . A system comprising: a processor comprising: a first die including a first core and a second core; a second die including a first portion of an in-package memory; a third die including a second portion of the in-package memory; and wherein the processor is to be partitioned into: a first node having the first core and associated with a first portion of a platform memory coupled to the processor; a second node having the second core and associated with a second portion of the platform memory; a third node having the first portion of the in-package memory; and a fourth node having the second portion of the in-package memory, wherein the in-package memory and the platform memory comprise a common address space; and the platform memory coupled to the processor.

Claim 20

Dependent Claim 132 words

17 . A system comprising: a processor comprising: a first die including a first core and a second core; a second die including a first portion of an in-package memory; a third die including a second portion of the in-package memory; and wherein the processor is to be partitioned into: a first node having the first core and associated with a first portion of a platform memory coupled to the processor; a second node having the second core and associated with a second portion of the platform memory; a third node having the first portion of the in-package memory; and a fourth node having the second portion of the in-package memory, wherein the in-package memory and the platform memory comprise a common address space; and the platform memory coupled to the processor.

Claim 21

Dependent Claim 79 words

18 . The system of claim 17 , wherein the first core and the first portion of the platform memory are to be associated with a first distance indicator and the first core and the first portion of the in-package memory are to be associated with a second distance indicator, the second distance indicator to indicate the first portion of the in-package memory as being more distant to the first core than the first portion of the platform memory.

Claim 22

Dependent Claim 89 words

19 . The system of claim 17 , wherein the processor further comprises a first memory controller coupled to the first portion of the in-package memory and a second memory controller coupled to the first portion of the platform memory, wherein the second memory controller is to enable at least part of the first portion of the platform memory to accommodate an operating system allocation and the first memory controller is to enable at least part of the first portion of the in-package memory to accommodate a user allocation.

Claim 23

Dependent Claim 90 words

20 . The system of claim 17 , wherein in a first memory mode the in-package memory is to be a cache memory for the platform memory, in a second memory mode the in-package memory and the platform memory comprise the common address space, and in a third memory mode at least the first portion of the in-package memory is to be the cache memory for the platform memory and at least the second portion of the in-package memory is to form the common address space with the platform memory.

Providing multiple memory modes for a processor including internal memory

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag