US9384152B2
Active / In Force
US
⏱️ 4.1 years remaining
Coordinating memory operations using memory-device generated reference signals
Assignee: Rambus Inc
•
Filing: 2010-12-01
•
Granted: 2016-07-05
•
Expires: 2030-12-01
Abstract
Abstract A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.
Inventors
- 👤 Scott C. Best
- 👤 Ian Shaeffer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:04
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/061; G06F3/0628; G06F3/0655; G06F3/0659; G06F3/0668; G06F3/0671; G06F3/0683; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4093; Y02B60/1228; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
123 words
A memory system, comprising: a memory controller; and a memory die coupled to the memory controller and comprising: a memory data interface having a data pin coupled to the memory controller; a data output circuit coupled to the data pin to transmit read data from the memory die to the memory controller, the data output circuit having a timing input to receive a timing-reference signal to time the transmitted read data; and an integrated oscillator to generate the timing-reference signal within the memory die, the oscillator including at least one physical die structure that determines a frequency of the timing-reference signal, wherein the memory die is operable to coordinate a memory read operation with the memory controller and timed to the timing-reference signal.
Claim 2
Dependent Claim
123 words
A memory system, comprising: a memory controller; and a memory die coupled to the memory controller and comprising: a memory data interface having a data pin coupled to the memory controller; a data output circuit coupled to the data pin to transmit read data from the memory die to the memory controller, the data output circuit having a timing input to receive a timing-reference signal to time the transmitted read data; and an integrated oscillator to generate the timing-reference signal within the memory die, the oscillator including at least one physical die structure that determines a frequency of the timing-reference signal, wherein the memory die is operable to coordinate a memory read operation with the memory controller and timed to the timing-reference signal.
Claim 3
Dependent Claim
33 words
The memory system of claim 1 , further comprising a reference transmitter to derive a shared reference signal from the timing-reference signal and to transmit the shared reference signal to the memory controller.
Claim 4
Dependent Claim
35 words
The memory system of claim 2 , wherein the reference transmitter transmits the shared reference signal to the memory controller via a dedicated, conductive reference signal path between the memory die and the memory controller.
Claim 5
Dependent Claim
28 words
The memory system of claim 2 , wherein the memory die is operable to divide down the frequency of the timing-reference signal to create the shared reference signal.
Claim 6
Dependent Claim
29 words
The memory system of claim 2 , wherein the memory controller is operable to coordinate at least one controller operation with the memory die based on the timing-reference signal.
Claim 7
Dependent Claim
27 words
The memory system of claim 2 , wherein the memory controller is operable to transmit write data to the memory die based on the shared reference signal.
Claim 8
Dependent Claim
28 words
The memory system of claim 6 , wherein the memory controller is operable to transmit a controller command to the memory die based on a processor reference signal.
Claim 9
Dependent Claim
28 words
The memory system of claim 7 , wherein the memory die further includes a memory core to perform a memory core operation based on the processor reference signal.
Claim 10
Dependent Claim
34 words
The memory system of claim 7 , wherein the memory die further includes a memory core, and wherein the memory die is operable to perform a memory core operation based on the timing-reference signal.
Claim 11
Dependent Claim
53 words
The memory system of claim 9 , wherein the memory controller is operable to program the memory die to generate the shared reference signal based on an approximate frequency ratio between the shared reference signal and the processor reference signal and to perform the memory core operation based on the shared reference signal.
Claim 12
Dependent Claim
15 words
The memory system of claim 10 , wherein the approximate frequency ratio is an integer.
Claim 13
Dependent Claim
28 words
The memory system of claim 6 , wherein the memory controller is operable to transmit a controller command to the memory die based on the shared reference signal.
Claim 14
Dependent Claim
58 words
The memory system of claim 12 , wherein the memory controller is operable to generate a divided down version of the timing-reference signal based on an approximate frequency ratio between the timing-reference signal and a processor reference signal and to transmit the controller command to the memory die based on the divided down version of the timing-reference signal.
Claim 15
Dependent Claim
42 words
The memory system of claim 13 , wherein the memory controller is operable to program the memory die to generate the shared reference signal and the memory die is operable to perform a memory core operation based on the shared reference signal.
Claim 16
Dependent Claim
15 words
The memory system of claim 13 , wherein the approximate frequency ratio is an integer.
Claim 17
Dependent Claim
16 words
The memory system of claim 1 , wherein the memory die comprises dynamic random access memory.
Claim 18
Dependent Claim
15 words
The memory system of claim 1 , wherein the oscillator comprises an LC clock circuit.
Claim 19
Dependent Claim
24 words
The memory system of claim 1 , wherein the memory die and the memory controller are embodied in first and second integrated circuits, respectively.
Claim 20
Dependent Claim
24 words
The memory system of claim 1 , wherein a combination of the memory die and the memory controller are embodied as a memory module.
Claim 21
Dependent Claim
16 words
The memory system of claim 1 , wherein the oscillator comprises a resonant LC oscillator circuit.
Claim 22
Dependent Claim
59 words
A memory die comprising: a memory core; a memory physical interface communicatively coupled to the memory core; and an integrated oscillator operable to generate an internal reference signal of a frequency defined by a physical die structure of the memory die, the memory physical interface to transmit read data to an external die based on the internal reference signal.
Claim 23
Dependent Claim
59 words
A memory die comprising: a memory core; a memory physical interface communicatively coupled to the memory core; and an integrated oscillator operable to generate an internal reference signal of a frequency defined by a physical die structure of the memory die, the memory physical interface to transmit read data to an external die based on the internal reference signal.
Claim 24
Dependent Claim
44 words
The memory die of claim 21 , wherein the memory physical interface comprises a reference transmitter coupled to the oscillator, the reference transmitter to derive a shared reference signal from the internal reference signal and transmit the shared reference signal to the external die.
Claim 25
Dependent Claim
16 words
The memory die of claim 22 , wherein the shared reference signal is a periodic signal.
Claim 26
Dependent Claim
26 words
The memory die of claim 22 , wherein the shared reference signal has a shared frequency that is an integer fraction of the internal reference signal.
Claim 27
Dependent Claim
39 words
The memory die of claim 22 , wherein the memory physical interface comprises a memory data interface operable to receive write data that has been transmitted from the external die at second frequency derived from the internal reference signal.
Claim 28
Dependent Claim
35 words
The memory die of claim 25 , wherein the memory physical interface comprises a memory command interface operable to receive an external die command transmitted from the external die based on an external reference signal.
Claim 29
Dependent Claim
39 words
The memory die of claim 26 , wherein the memory physical interface is operable to receive the external reference signal and the memory die is operable to perform a memory core operation based on the received external reference signal.
Claim 30
Dependent Claim
25 words
The memory die of claim 26 , wherein the memory die is operable to perform a memory core operation based on the internal reference signal.
Claim 31
Dependent Claim
53 words
The memory die of claim 28 , wherein the external reference signal is of an external-reference frequency, and wherein the memory die comprises a core clock circuit operable to be programmed by the external die to divide the frequency of the internal reference signal to create a timing reference of the external-reference frequency.
Claim 32
Dependent Claim
27 words
The memory die of claim 29 , wherein the approximate ratio between the frequency of the internal reference signal and the external reference frequency is an integer.
Claim 33
Dependent Claim
53 words
The memory die of claim 25 , wherein the memory physical interface comprises a memory command interface operable to receive an external die command that has been transmitted from the external die at a bit rate, and wherein the frequency of the internal reference signal is an integer multiple of the bit rate.
Claim 34
Dependent Claim
14 words
The memory die of claim 31 , wherein the integer is greater than one.
Claim 35
Dependent Claim
36 words
The memory die of claim 32 , wherein the memory physical interface comprises a core clock circuit operable to be programmed by the external die to generate a divided down version of the internal reference signal.
Claim 36
Dependent Claim
32 words
The memory die of claim 21 , wherein the die structure includes an inductor of inductance L and exhibits a capacitance C, and wherein the frequency is the square root of 1/LC.
Claim 37
Dependent Claim
16 words
The memory die of claim 21 , wherein the memory die is a DRAM integrated circuit.
Claim 38
Dependent Claim
21 words
The memory die of claim 21 , wherein the memory die is instantiated on a memory module with the external die.
References Cited (Backward Citations)
US6353559B2
Cited
US20040236910A1
Cited
US20030231537A1
Cited
US20070255919A1
Cited
US7071757B2
Cited
US6768693B2
Cited
US20040078510A1
Cited
US20060236105A1
Cited
US20060280015A1
Cited
US20070101086A1
Cited
US20090077423A1
Cited
US20100118632A1
Cited
US20100164476A1
Cited
US20110241787A1
Cited
US20130145084A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2019-07-05 | 2020-01-04 | 2020-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2023-07-05 | 2024-01-04 | 2024-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2027-07-05 | 2028-01-04 | 2028-07-05 | $7700.00 | Pending Window |