Microprocessor and debug system

Claim 2

A debug system comprising: a debug tool having a monitor program for debugging a user target system; a microprocessor having a processor core for executing one of a user program and the monitor program and a debug module connected to the processor core through at least one of an internal debug interface and a processor bus and to said debug tool through an external debug interface, the debug module having interface means serving as an interface with said debug tool so that the processor core may execute the monitor program and control means for requesting the processor core for one of an interrupt and an execution to switch the processor core from the user program to the monitor program; a memory connected to said microprocessor through the processor bus in the user target system, for storing information necessary for said microprocessor to execute the user program; and an I/O unit connected to said microprocessor through the processor bus in the user target system.

Claim 3

The microprocessor according to claim 1, wherein said debug module has: a break circuit for comparing the address of an instruction or data provided by said processor core with a preset address or data, and if they coincide with each other, sending an address break exception request to said processor core; a tracer for processing program counter trace information provided by said processor core and providing the processed information; a processor bus break circuit connected to said processor core through the processor bus, for monitoring bus cycles in the processor bus, and if a bus cycle for preset address and data is executed, sending an exception request to said processor core; a serial monitor bus circuit connected to said processor core through the processor bus, serving as an interface with the debug tool when said processor core executes the monitor program stored in the debug tool; a register circuit for storing information to control the functions of said debug module, the information being accessed by said processor core; an external interface circuit serving as an interface for the tracer, serial monitor bus circuit, and processor core with the debug tool; and a clock signal generator for providing the debug tool with a clock signal that defines the transfer speed of signals transmitted between the microprocessor and the debug tool.

Claim 4

The microprocessor according to claim 3, wherein the clock signal generator supplies a clock signal whose frequency is a multiple of or a power of 2 of the frequency of a clock signal that drives said processor core.

Claim 5

The microprocessor according to claim 1, wherein said debug module is connected to the debug tool with dedicated signals.

Claim 6

The microprocessor according to claim 1, wherein said debug module is connected to the debug tool with unidirectional signals.

Claim 7

The microprocessor according to claim 1, wherein: when said processor core accesses a specific area, said debug module sequentially transfers address and bus control signals from said processor core to the debug tool at predetermined intervals; if the access to the specific area is a write access, said debug module sequentially transfers data signals to the debug tool at predetermined intervals; and if the access to the specific area is a read access, said debug module sequentially receives signals from the debug tool at predetermined intervals, forms a multi-bit data signal, and sends the data signal to said processor core.

Claim 8

The microprocessor according to claim 7, wherein the predetermined intervals are defined according to the output clock signal of a clock signal generator.

Claim 9

The microprocessor according to claim 1, wherein said debug module transfers bus interface signals from said processor core to the debug tool through a first transfer line bit by bit in series, and the debug tool transfers information to said debug module through a second transfer line bit by bit in series.

Claim 10

The microprocessor according to claim 1, wherein: said processor core has a mode signal to be enabled when an exception or reset request for starting the monitor program is made; and said debug module allows said processor core to access the debug tool or a register circuit in said debug module only when the mode signal is enabled.

Claim 11

The microprocessor according to claim 1, wherein: said processor core has a mode signal to be enabled when an exception or reset request for starting the monitor program is made; and said debug module has a control bit that prohibits, when enabled, said processor core from accessing the debug tool or a register circuit in said debug module even if the mode signal is enabled.

Claim 12

The microprocessor according to claim 1, wherein said processor core has: a mode that is enabled when an exception or reset request for starting the monitor program is made; a first write instruction to provide the value of a general register as a data signal and enable a first write signal; and a second write instruction to provide the value of the general register as a data signal and enable a second write signal.

Claim 13

The microprocessor according to claim 12, wherein: said debug module has a control bit for prohibiting said processor core from accessing said debug module; a write access to said debug module according to the first write signal is prohibited if the control bit is enabled; and a write access to said debug module according to the second write signal is enabled without regard to the control bit.

Claim 14

A microprocessor comprising: a processor core for executing a program; and a program counter tracer connected to said processor core through an internal debug interface, for providing a program counter signal that represents the address of an instruction executed by said processor core, the number of lines that transmit the program counter signal being smaller than the number of bits of the address.

Claim 15

The microprocessor according to claim 14, wherein: said processor core asserts an indirect jump signal when executing an indirect jump instruction and provides said program counter tracer with the target address of the indirect jump instruction; and upon receiving the asserted indirect jump signal, said program counter tracer accepts the target address, transmits the target address as the program counter signal from a lower bit thereof, and provides a program counter status signal indicating that the transmission of the target address has started.

Claim 16

The microprocessor according to claim 14, wherein: said processor core asserts an exception signal when an exception occurs and provides said program counter tracer with the target address of the exception; and upon receiving the asserted exception signal, said program counter tracer accepts the target address, encodes the target address into information whose number of bits is smaller than that of the target address, transmits the coded information as the program counter signal, and provides a program counter status signal indicating that the transmission of the target address has started.

Claim 17

The microprocessor according to claim 15, wherein, when said processor core executes a second indirect jump instruction while said program counter tracer is transmitting the target address of a first indirect jump instruction: said processor core asserts the indirect jump signal when executing the second indirect jump instruction and provides said program counter tracer with the target address of the second indirect jump instruction; and upon receiving the asserted indirect jump signal, said program counter tracer accepts the target address of the second indirect jump instruction, stops transmitting the target address of the first indirect jump instruction, transmits the target address of the second indirect jump instruction as the program counter signal, and provides a program counter status signal indicating that the transmission of the target address has started.

Claim 18

The microprocessor according to claim 15, wherein, when an exception occurs while said program counter tracer is transmitting the target address of an indirect jump instruction: said processor core asserts an exception signal indicating that the exception has occurred and provides said program counter tracer with the target address of the exception; and upon receiving the asserted exception signal, said program counter tracer accepts the target address, suspends the transmission of the target address of the indirect jump instruction, encodes the target address of the exception into information whose number of bits is smaller than that of the target address, transmits the coded information as the program counter signal, provides a program counter status signal indicating that the transmission of the target address of the exception has started, and after the transmission of the coded information is complete, resumes the transmission of the target address of the indirect jump instruction.

Claim 19

The microprocessor according to claim 14, wherein: said processor core asserts a direct jump signal when executing a direct jump instruction or a taken conditional branch instruction and provides said program counter tracer with the target address of the direct jump instruction or branch instruction; if said program counter tracer is not transmitting the target address of an indirect jump instruction when receiving the asserted direct jump signal, said program counter tracer accepts the target address from said processor core, transmits the target address as the program counter signal from a lower bit thereof, provides a program counter status signal indicating that the transmission of the target address has started; and if said program counter tracer is transmitting the target address of an indirect jump instruction when receiving the asserted direct jump signal, said program counter tracer only provides a program counter status signal indicating that the direct jump instruction or taken conditional branch instruction has been executed,

Claim 20

The microprocessor according to claim 14, wherein: said processor core asserts a pipeline signal when executing an instruction; when the pipeline signal is asserted and is received by said program counter tracer, said program counter tracer provides a program counter status signal indicating that the instruction has been executed by said processor core; and when the pipeline signal is not asserted and is received by said program counter tracer, said program counter tracer provides a program counter status signal indicating that the instruction has not been executed.

Claim 21

The microprocessor according to claim 14, wherein, when said processor core executes a second indirect jump instruction while said program counter tracer is transmitting the target address of a first indirect jump instruction: said processor core asserts an indirect jump signal when executing the second indirect jump instruction, provides said program counter tracer with the target address of the second indirect jump instruction, and if a processor core stop signal is asserted, suspends the execution of the second indirect jump instruction; and said program counter tracer asserts the processor core stop signal when the indirect jump signal for the second indirect jump instruction is asserted, completes the transmission of the target address of the first jump instruction, accepts the target address of the second indirect jump instruction from said processor core, transmits the target address of the second indirect jump instruction as the program counter signal, and provides a program counter status signal indicating that the transmission of the target address has started.

Claim 22

The microprocessor according to claim 14, wherein, when said processor core executes a second indirect jump instruction while said program counter tracer is transmitting the target address of a first indirect jump instruction: said processor core asserts an indirect jump signal when executing the second indirect jump instruction, provides said program counter tracer with the target address of the second indirect jump instruction, and if a processor core stop signal is asserted, suspends the execution of the second indirect jump instruction; said program counter tracer waits for a trace mode signal indicating whether or not the transmission of the target address of the first indirect jump instruction must be completed; when the trace mode signal indicates to complete the transmission, said program counter tracer asserts the processor core stop signal in response to the asserted indirect jump signal for the second indirect jump instruction, completes the transmission of the target address of the first indirect jump instruction, accepts the target address of the second indirect jump instruction from said processor core, transmits the target address of the second indirect jump instruction as the program counter signal, and provides a program counter status signal indicating that the transmission of the target address has started; and when the trace mode signal indicates not to complete the transmission, said program counter tracer accepts the target address of the second indirect jump instruction from said processor core in response to the asserted indirect jump signal for the second indirect jump instruction, stops the transmission of the target address of the first indirect jump instruction, transmits the target address of the second indirect jump instruction as the program counter signal, and provides a program counter status signal indicating that the transmission of the target address has started.

Claim 23

The microprocessor according to claim 14, wherein: if an interrupt or exception is externally requested to switch said processor core from a user program to a monitor program for debugging a user target system, said processor core suspends the user program, jumps to the monitor program, and fetches instructions of the monitor program; and if said program counter tracer is transmitting the target address of a jump instruction or an exception code when said processor core jumps to the monitor program, said processor core delays the fetching of the instructions of the monitor program until said program counter tracer completes the transmission.

Claim 24

A microprocessor comprising: a processor core for executing a program; a break circuit for making a break request or asserting a trigger request signal to said processor core when an accessed address coincides with a set address, or when an accessed address and data coincide with a set address and data; and a program counter tracer for providing an external status signal indicating that the trigger request signal has been asserted after said break circuit asserts the same.

Claim 25

The microprocessor according to claim 24, wherein said program counter tracer encodes the internal state of said processor core and provides an external status signal indicating the encoded internal state, when said processor core is in a first internal state and when the trigger request signal is asserted, said program counter tracer provides an external status signal indicating an internal state of no trigger request without regard to the asserted trigger request signal, and when said processor core is in a second internal state and when the trigger request signal is asserted, said program counter tracer provides an external status signal indicating that the trigger request has been made.

Claim 26

The microprocessor according to claim 25, wherein the first internal state corresponds to executing a jump instruction or producing an exception, and the second internal status corresponds to sequentially executing instructions or causing a pipeline stall.