EP0313848A2
Expired / Lapsed
EP
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Data processor with development support features
Assignee: Motorola Solutions Inc
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Filing: 1988-09-29
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Granted: —
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Expires: 2008-09-29
Abstract
Abstract A data processor (11) with development support features includes an alternate mode of operation in which instructions are received by means of an externally-controlled path. The connections used by the externally-controlled path are not shared by any system resources accessible to the data processor (11) in the normal mode of operation, but are used by other development support features in the normal mode. In a preferred embodiment, an integrated circuit microcomputer (10) includes such a data processor (11) as its CPU. The CPU (11) has access to on-chip peripherals and memory, in addition to off-chip peripherals (13,15) and memory (14), in both the normal and alternate modes of operation, by means of a parallel bus (12) which it operates as a bus master. In the alternate mode, the CPU receives instructions by means of a serial bus on which the CPU is a slave device.
Inventors
- 👤 John J. Vaglica
- 👤 Jay A. Hartvigsen
- 👤 Rand L. Gray
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 06:14
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F9/30003; G06F9/3005; G06F9/32; G06F9/322; G06F9/323; G06F11/22; G06F11/2205; G06F11/2236
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
170 words
A data processor (11) having first and second modes of operation for use in a data processing system (10) comprising a parallel communication bus (12)and a serial communication bus, the data processor (11) further comprising first means (51, 52, 53, 54) for sequentially executing a first plurality of instructions fetched from a memory (14) by means of the parallel communication bus (12) while in the first mode and second means (51, 52, 53, 54, 55) for sequentially executing a second plurality of instructions received by means of the serial communication interface while in the second mode, the data processor (11) being further characterized by: mode switch means for switching between the first and second modes of operation, the mode switch means being responsive to at least one of the second plurality of instructions to switch from the second mode of operation to the first mode of operation; and control means for disabling the mode switch means from switching from the first mode of operation to the second mode of operation.
Claim 2
Dependent Claim
170 words
A data processor (11) having first and second modes of operation for use in a data processing system (10) comprising a parallel communication bus (12)and a serial communication bus, the data processor (11) further comprising first means (51, 52, 53, 54) for sequentially executing a first plurality of instructions fetched from a memory (14) by means of the parallel communication bus (12) while in the first mode and second means (51, 52, 53, 54, 55) for sequentially executing a second plurality of instructions received by means of the serial communication interface while in the second mode, the data processor (11) being further characterized by: mode switch means for switching between the first and second modes of operation, the mode switch means being responsive to at least one of the second plurality of instructions to switch from the second mode of operation to the first mode of operation; and control means for disabling the mode switch means from switching from the first mode of operation to the second mode of operation.
Claim 3
Dependent Claim
36 words
A data processor according to claim 1 wherein the mode switch means is further characterized as being responsive to an error condition to switch from the first mode of operation to the second mode of operation.
Claim 4
Dependent Claim
45 words
A data processor according to claim 1 or claim 2 wherein the mode switch means is further characterized as being responsive to at least one of the first plurality of instructions to switch from the first mode of operation to the second mode of operation.
Claim 5
Dependent Claim
119 words
A data processor (11) comprising execution means (51, 52, 53, 54) for sequentially executing a plurality of instructions, the execution means (51, 52, 53, 54) having a first mode in which instructions of a first subset are excecuted and a second mode in which instructions of a second subset are executed, and communication means (50, 55) for providing the plurality of instructions to the execution means and mode switch means for switching between the first and second modes of operation, the data processor being further characterized in that: the communication means operates in a master mode while the execution means is in the first mode and in a slave mode while the execution means is in the second mode.
Claim 6
Dependent Claim
119 words
A data processor (11) comprising execution means (51, 52, 53, 54) for sequentially executing a plurality of instructions, the execution means (51, 52, 53, 54) having a first mode in which instructions of a first subset are excecuted and a second mode in which instructions of a second subset are executed, and communication means (50, 55) for providing the plurality of instructions to the execution means and mode switch means for switching between the first and second modes of operation, the data processor being further characterized in that: the communication means operates in a master mode while the execution means is in the first mode and in a slave mode while the execution means is in the second mode.
Claim 7
Dependent Claim
38 words
A data processor (11) according to claim 4 wherein the communication means is further characterized as comprising: controller means (50) for operating a parallel communication bus as a bus master; and a slave only serial communication interface (55).
Claim 8
Dependent Claim
60 words
A data processor (11) according to claim 4 or claim 5 wherein the mode switch means is further characterized as: being responsive to an externally-provided signal to switch from the first mode to the second mode; and being responsive to at least one of the instructions of the second subset to switch from the second mode to the first mode.
Claim 9
Dependent Claim
40 words
A data processor (11) according to claim 6 wherein the mode switch means if further characterized as: being responsive to at least one of the instructions of the first subset to switch from the first mode to the second mode.
Claim 10
Dependent Claim
33 words
A data processor (11) according to claim 7 wherein the mode switch means is further characterized as: being responsive to an error condition to switch from the first mode to the second mode.
References Cited (Backward Citations)
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