EP0453268A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A microprocessor for inserting a bus cycle to output an internal information for an emulation
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1991-04-17
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Granted: —
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Expires: 2011-04-17
Abstract
Abstract A microprocessor having a buffer (10) or memory capable of holding a plurality of instructions in advance has a function to permitting the insertion of a special bus cycle for outputting the internal information of the microprocessor externally of the microprocessor in a predetermined operation mode at the time of each execution. The information inside the microprocessor, which is to be outputted to the exterior in the special bus cycle, is exemplified by the address of the executed instruction in a memory space, an instruction code or the code for identifying said executed instruction in the instruction group prefetched. In the emulation of the system using the instruction prefetch type microprocessor, according to the means described above, the instruction that has been executed can be easily known from the exterior so that an accurate emulation analysis is possible and facilitating the analysis of the trace data thereby to improve the debugging efficiency.
Inventors
- 👤 Shigezumi Matsui
- 👤 Ikuya Kawasaki
- 👤 Yoshiyuki Kondo
- 👤 Kouji Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 19:34
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/28; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; G06F11/3648; G06F11/3652; G06F11/22; G06F11/26; G06F11/261; G06F11/30; G06F11/34
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
159 words
A microprocessor comprising: (a) an instruction buffer (10) for holding a plurality of said instruction words fetched from memory; (b) an instruction decoder (13) coupled to said instruction buffer for decoding said instruction word and providing a decoded result; (c) at least one instruction execution unit (20) coupled to said instruction decoder, including an operation device and registers for executing said instruction; (d) an address controller (15) coupled to said instruction execution unit (20), including an instruction fetch pointer for identifying an address; (e) a bus control circuit (11,19) coupled to said instruction buffer (10), said instruction execution unit (20) and said address controller (15) for inserting a bus cycle for outputting internal information of said microprocessor in accordance with a special bus cycle request signal; wherein (f) said instruction buffer (10) said instruction decoder (13) said instruction execution unit (20) said address controller (15) and said bus control circuit (11,19) all being constructed in a single semiconductor device.
Claim 2
Dependent Claim
29 words
A microprocessor of claim 1 wherein said bus control circuit (11,19) comprises a circuit (14) for inserting said bus cycle of outputting said internal information indicating an executing instruction.
Claim 3
Dependent Claim
37 words
A microprocessor according to claim 2 or 3 wherein said circuit includes control means for operating in accordance with an end signal for indicating the end of said executing instruction and said special bus cycle request signal.
Claim 4
Dependent Claim
30 words
A microprocessor of any one of claims 1 to 3 wherein said special bus cycle request signal is provided by an external source or an internal source in said microprocessor.
Claim 5
Dependent Claim
25 words
A microprocessor according to any one of the preceding claims, wherein the address controller is also coupled to the instruction buffer and the instruction decoder.
Claim 6
Dependent Claim
51 words
A microprocessor according to any one of the preceding claims, wherein the memory is an external memory, the microprocessor is arranged to pre-fetch a plurality of instruction words from the external memory, and the address controller is arranged to hold an address for fetching the instruction words from the external memory.
Claim 7
Dependent Claim
31 words
A microprocessor according to any one of claims 1 to 5, having a plurality of said execution units, and the microprocessor is arranged to execute a plurality of instructions in parallel.
Claim 8
Dependent Claim
23 words
A microprocessor according to any one of claims 1 to 5 and 7, wherein the memory is an internal memory of the microprocessor.
Claim 9
Dependent Claim
31 words
A microcomputer according to claim 8, wherein the internal memory is in the same semiconductor device as the instruction buffer, instruction decoder, instruction execution unit, address controller and bus control circuit.
Claim 10
Dependent Claim
36 words
A microprocessor according to claim 8 or claim 9 wherein the internal memory is arranged to store a plurality of instructions and the instruction fetch pointer holds an address for fetching instructions from the internal memory.
Claim 11
Dependent Claim
103 words
An in-circuit emulator for emulating a system used in a microprocessor for prefetching a plurality of instructions, including an emulation microprocessor; wherein said emulation microprocessor is according to any one of the preceding claims; and said in-circuit emulator includes: (i) a trace memory for sampling and storing a signal on a bus in said system; (ii) an emulation control unit for improving an emulation or debugging function; (iii) a break point control unit for setting a condition for storing an execution of a program or stopping a trace to interrupt a program; and (iv) an emulation memory for using a said system memory.
Claim 12
Independent Claim
90 words
A system including a microprocessor for prefetching a plurality of instructions; wherein said microprocessor is according to any one of claims 1 to 10; and instruction execution unit, said address controller, and said bus control circuit, all being constructed in a single semiconductor and system includes: (i) said external memory for storing said instructions and data; (ii) a peripheral device having a hard disc controller; and (iii) a system bus coupled said microprocessor, said external memory, said peripheral device, having an address bus, a data bus and a control bus.
References Cited (Backward Citations)
No citation records indexed.
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