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EP0712082A1
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Method and apparatus for adaptive circular predictive buffer management
Assignee: International Business Machines Corp
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Filing: 1995-09-29
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Granted: —
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Expires: 2015-09-29
Abstract
Abstract A system for adaptively managing predictive buffer memory prefetching operations to optimize buffer memory hits in a data storage system. The arriving data access request (DAR) stream is monitored for a particular data access pattern and, when a sequential access pattern is detected (60), the buffer memory prefetching storage rule is switched (62) to a circular overwrite mode to achieve the best sequential access performance. When the sequential access pattern disappears, a nonsequential access pattern is detected and the buffer memory prefetching storage rule is responsively switched (68) to a non-sequential or block overwrite mode to maximize data block "re-use" hits in the data buffer. Sequential access pattern detection is achieved using a threshold that may be adapted to the size of incoming DARs. The buffer memory may be organized in many smaller segments, each operated independently according to the system of this invention, to provide simultaneous optimal predictive buffering for multiple processing threads.
Inventors
- 👤 Wah-Fung Ng Spencer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 14:17
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F13/00; G06F5/00; G06F5/06; G06F12/0866; G06F12/12; G06F12/121; G06F12/126; G06F12/127; G06F2212/00; G06F2212/60; G06F2212/6026
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
216 words
A method for operating a buffer memory (26) in a data storage system (10) having a primary storage means (12-16) for storing a sequence of data blocks coupled to said buffer memory (26) through a controller means (24) for reading and storing in said buffer memory (26) each of one or more said data blocks requested by a data access request (DAR) from a processor input/output (I/O) means (28) wherein said DAR is the latest of an uninterruptedly consecutive DAR sequence having an access pattern, said controller means (24) having means for prefetching a consecutive plurality of said data blocks stored subsequently in said primary storage means (12-16) to said one or more requested data blocks and having means for storing said consecutive data block plurality in said buffer memory (26) in either a block overwrite mode (BOM) or a circular overwrite mode (COM), said method comprising the steps of: (a) detecting (56-60) either a sequential said access pattern (SAP) or a nonsequential said access pattern (NAP) in said DAR sequence; (b) switching (62) said buffer memory storing means (36) to said circular overwrite mode (COM) responsive to a detection of said SAP; and (c) switching (68) said buffer memory storing means (36) to said block overwrite mode (BOM) responsive to a detection of said NAP.
Claim 2
Dependent Claim
59 words
The method of claim 1 wherein said detecting step (a) comprises the steps of: (a.1) selecting a predetermined threshold for consecutive DARs; (a.2) counting (58) the number of said consecutive DARs received in said uninterruptedly consecutive DAR sequence; and (a.3) producing (60) said SAP detection when said consecutive DAR number exceeds said predetermined threshold, otherwise producing said NAP detection.
Claim 3
Dependent Claim
30 words
The method of claim 2 wherein said selecting step (a.1) comprises the step of: (a.1.1) changing said predetermined threshold responsive to the number of data blocks requested by said DAR.
Claim 4
Independent Claim
68 words
The method of any claim from 1 to 3 wherein said means for prefetching includes means for completing the prefetch of a minimum number of said data blocks before interruption and said first switching step (b) comprises the steps of: (b.1) prefetching a predetermined plurality of said data blocks for storage in said BOM; and (b.2) prefetching a plurality of said data blocks for storage in said COM.
Claim 5
Independent Claim
54 words
The method of any claim from 1 to 4 wherein said buffer memory (26) includes a plurality of memory segments (32) each independently operated such that an active said buffer memory segment (32) is switched to said COM responsive to said SAP detection and is switched to said BOM responsive to said NAP detection.
Claim 6
Dependent Claim
259 words
A buffer memory controller (24) coupled to a buffer memory (26) in a data storage system (10) having a primary storage means (12-16) for storing a sequence of data blocks coupled to said buffer memory (26) through said buffer memory controller (24) and having means for accepting a plurality of data access requests (DARs) from a processor I/O controller (28), wherein said each DAR is the latest of an uninterruptedly consecutive DAR sequence having an access pattern, said buffer memory controller (24) comprising: fetching means coupled to said primary storage means (12-16) and said buffer memory (26) for reading and storing in said buffer memory (26) each of one or more said data blocks requested by said each DAR; prefetching means in said fetching means for reading and storing in said buffer memory (26) a consecutive plurality of said data blocks stored subsequently in said primary storage means (12-16) to said one or more data blocks requested by said each DAR, wherein said prefetching means stores said consecutive data block plurality in said buffer memory (26) in either a block overwrite mode (BOM) or a circular overwrite mode (COM); detecting means (56-60) coupled to said fetching means for detecting either a sequential access pattern (SAP) or a non-sequential access pattern (NAP) in each said uninterruptedly consecutive DAR sequence; and switching means (36) coupled to said prefetching means for switching (62) said prefetching means storage mode to said COM responsive to said SAP detection and for switching (68) said prefetching storing means to said BOM responsive to said NAP detection.
Claim 7
Dependent Claim
77 words
The buffer memory controller (24) of claim 6 wherein said detecting means comprises: selecting means for selecting a predetermined threshold for consecutive DARs; counting means (58) for counting the number of consecutive said DARs received in said each uninterruptedly consecutive DAR sequence; and comparing means (60) coupled to said selecting means and said counting means (58) for producing said SAP detection when said consecutive DAR number exceeds said predetermined threshold and for producing said NAP detection otherwise.
Claim 8
Dependent Claim
32 words
The buffer memory controller (24) of claim 7 wherein said selecting means comprises: means for changing said predetermined threshold responsive to the number of said data blocks requested by said each DAR.
Claim 9
Dependent Claim
34 words
The buffer memory controller (24) of any claim from 6 to 8 wherein said prefetching means comprises: minimum prefetching means for completing the prefetch of a minimum number of said data blocks before interruption.
Claim 10
Dependent Claim
44 words
The buffer memory controller (24) of any claim from 6 to 9 wherein said buffer memory (26) comprises: a plurality of memory segments (32) each independently operated in said COM responsive to said SAP detection and in said BOM responsive to said NAP detection.
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