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EP0301211A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Cache management for a peripheral data storage subsystem

Assignee: International Business Machines Corp
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Filing: 1988-06-10
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Granted: —
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Expires: 2008-06-10
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Abstract

Abstract The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indica­tion of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimised. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted. The examina­tion of the group of tracks units and the implementation of the data promotion and demotion (early cast-out) is synchronised which results in a synergistic effect for increasing throughput of the cache for sequentially-processed data. A limit of promotion is determined to create a window of sequential data processing.

Inventors

  • 👤 Gerald Ellsworth Tayler
  • 👤 Robert E. Wagner

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 19:46
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0866; G06F12/0862; G06F12/0888; G06F2212/00; G06F2212/31; G06F2212/312; G06F2212/60; G06F2212/6026

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 195 words
Data processing apparatus including a cache store operatively connected between a host processor and a backing store, in both of which stores, all data is addressable by track, each track is capable of storing an amount of data equal to a given number of data bits and the tracks in the cache store are addressable by the same addresses that are used to access the counterpart tracks in the backing store, the host processor accessing, or primarily accessing, the cache store for writing and reading both stores, and a cache controller determining the promotion and demotion of tracks between the cache and the backing store and arranged, in operation, to switch between promotion and demotion protocols in dependence on the result of a running analysis of the proportion of data in the currently accessed track and its connected previously accessed tracks actually referenced in relation to thresholds preset by the host, the controller, for each access to the cache store by the host processor, measuring the amount of data in that track that is referenced by the access and separately storing the measured amount as an access extent for that track or incorporating such thereinto.
Claim 2
Dependent Claim 195 words
Data processing apparatus including a cache store operatively connected between a host processor and a backing store, in both of which stores, all data is addressable by track, each track is capable of storing an amount of data equal to a given number of data bits and the tracks in the cache store are addressable by the same addresses that are used to access the counterpart tracks in the backing store, the host processor accessing, or primarily accessing, the cache store for writing and reading both stores, and a cache controller determining the promotion and demotion of tracks between the cache and the backing store and arranged, in operation, to switch between promotion and demotion protocols in dependence on the result of a running analysis of the proportion of data in the currently accessed track and its connected previously accessed tracks actually referenced in relation to thresholds preset by the host, the controller, for each access to the cache store by the host processor, measuring the amount of data in that track that is referenced by the access and separately storing the measured amount as an access extent for that track or incorporating such thereinto.
Claim 3
Dependent Claim 160 words
Apparatus as claimed in claim 1, wherein the host processor is arranged to send chains of access commands to the cache controller and for accesses invoked by any one such chain of commands, the controller compares the access extent for the current track with a first threshold value and, if it exceeds such first threshold value, reads all of the other access extents for tracks in the cache with backing store addresses lower than the address of the current track and which identify tracks accessed or, under hashing, that reasonably could have been accessed by the host processor in the chain before accessing the given track, separately compares all such with the first threshold value and if a predetermined number of such also exceed the first threshold value, sets a sequential indicator for the current track, the controller observing a "by track" protocol if the sequential indicator is not set and a prefetching protocol if the sequential indicator is set.
Claim 4
Dependent Claim 90 words
Apparatus as claimed in claim 2, wherein the controller, on setting the sequential indicator for the current track, combines the access extents involved to produce a combined access extent value and compares it with a preset combined threshold value, the controller, if the combined access extent value is not greater than the combined threshold value, generating an integral number proportional to the combined access extent to be representative of a sensed rate of I/O and promotes that number of prefetched tracks and sets the sequential indicator for each of them.
Claim 5
Dependent Claim 52 words
Apparatus as claimed in claim 3, wherein there is a cache bypass and the controller is arranged, if the combined access extent is greater than the combined access threshold, to reset the sequential indicator for the current track and switch promotion and demotion protocol to one in which the cache is bypassed.
Claim 6
Dependent Claim 104 words
Apparatus as claimed in claim 4, wherein track promotion and demotion takes place concurrently with data transfer between host processor and cache and, if the controller is observing the prefetch protocol and an access command is invoked relating to a track in the prefetch group being promoted which is not already in the cache, the actual data involved is sent via the bypass directly to the host processor, the amount of the data transferred being recorded, and is also promoted with the rest of the track or tracks, in due order, prior to re-analysis of the access statistics for promotion and demotion protocol determination.
Claim 7
Dependent Claim 48 words
Apparatus as claimed in claim 3 or any claim appendant thereto, wherein the combined access extent is generated by summing an integral number of predetermined ones of the read access extents and multiplying the sum by a look-ahead constant value which is a number not greater than ten.
Claim 8
Dependent Claim 39 words
Apparatus as claimed in claim 6, wherein the predetermined access extents are all access extents such that were any one of such to be less than the first threshold value, the sequential indicator would be prevented from being set.
Claim 9
Dependent Claim 106 words
Apparatus as claimed in claim 3 or any claim appendant thereto, wherein cache space for prefetched tracks is generated by demoting the data contents of tracks from the cache having backing store addresses contiguous but increasingly less than the backing store address of the given track and demoting the integral number of future tracks minus one from the cache store to the backing store beginning with a track having two backing store addresses less than the given track backing store address and proceeding to a track having an address equal to the address of the given track minus the integral number of tracks to be prefetched.
Claim 10
Dependent Claim 75 words
Apparatus as claimed in claim 8, wherein the host processor is adapted to send and the controller is adapted to receive and respond to a command defining an extent of host processor current permitted access to contiguous backing store tracks beginning with a first backing store address and ending with a second backing store address the promotion of prefetched tracks and demotion of lower addressed tracks being restricted to lie within the permitted access extent.
Claim 11
Dependent Claim 28 words
Apparatus as claimed in any preceding claim, wherein demotion is based upon least recently used criteria for operations below the established thresholds causing switching to the prefetching protocol.
Claim 12
Dependent Claim 70 words
Apparatus as claimed in any preceding claim wherein the cache store is a random access store and the backing store is comprised of plural rotating disk storage devices, the amounts of data actually accessed being measured and stored for accesses from the host processor to the cache store and for the cache store or backing store to the host processor, even when the addresses for the respective transfers are identical.
Claim 13
Dependent Claim 34 words
Apparatus as claimed in claim 2 or any claim appendant thereto wherein a sequential indicator can be set under instruction from the host processor in addition to being set by the controller performed analysis.
Claim 14
Dependent Claim 633 words
In a data storage system having attachment means for attaching the data storing system to a host processor whereby data may be transferred between the host processor and the data storing system for storage and retrieval; data transfer means intercoupling the attachment means, the cache store and the backing store so that data may be transferred directly between either of the stores and the attachment means or between the two stores; a programmed control connected to the attachment means, the data transfer means and the two stores for sending control signals thereto and receiving command and status signals therefrom such that the programmed control controls the operations of the data storing system; the programmed control including a control store for storing computer program indicia for sensing same and responding to the sensed indicia to send out the control signals and to sense and analyse the received command and status signals; the stores each having addressable data storing tracks of equal data-storage capacity; means in the programmed control stored computer program indicia to cause the programmed control to allocate predetermined ones of the cache tracks to store data addressably stored for predetermined respective ones of the backing store tracks; and means in the cache store for addressing the allocated cache tracks using the addresses of the predetermined respective ones of the tracks in the backing store: monitoring program indicia in the control store for being sensed by the programmed control for executing computer programming contained in such indicia for causing the programmed control for operating the system to monitor the data transfers between the attachment means and the cache store addressed ones of the allocated cache tracks for measuring the length of data in each such transfer and storing the measured data lengths, then summing the measured data lengths for all data transfers between the attachment means and the respective cache tracks to create a stored access extent for each of the cache tracks allocated to store data; threshold indicia in the control store for indicating a threshold value and being sensible by the programmed control for obtaining the threshold value; indicator means in the data transfer means for indicating a completion of a last data transfer between the cache store and the attachment means and the backing store address for the cache track used in the data transfer; comparison program indicia in the control store for being sensed by the programmed control for executing computer programming contained is such indicia causing the programmed control to operate the system for sensing the completion indicator and responding thereto sensing the stored access extents for the cache track used in the last data transfer and for "K" cache tracks respectively addressable by backing store addresses contiguous with the backing store address for the last access cache track, then the programmed control processing the sensed stored access extents using predetermined calculations to create an intermediate value is greater than the threshold value, indicating a sequential mode of operation for data transfers in the last accessed cache track, wherein "K" is an integer; and data promotion program indicia in the control store for being sensed by the programmed control for executing computer programming contained in such indicia for causing the programmed control to operate the system for sensing the sequential indicator, if the sequential indicator is set, then causing the programmed control to operate the system for promoting data from next backing store tracks to cache store tracks with the tracks having backing store address contiguous with and greater than the backing store address of the last accessed cache track, calculating the number of tracks to be promoted by sensing the intermediate value and changing the intermediate value by predetermined calculations, then activating the data transfer means for promoting the data stored in the next backing store tracks.
Claim 15
Dependent Claim 633 words
In a data storage system having attachment means for attaching the data storing system to a host processor whereby data may be transferred between the host processor and the data storing system for storage and retrieval; data transfer means intercoupling the attachment means, the cache store and the backing store so that data may be transferred directly between either of the stores and the attachment means or between the two stores; a programmed control connected to the attachment means, the data transfer means and the two stores for sending control signals thereto and receiving command and status signals therefrom such that the programmed control controls the operations of the data storing system; the programmed control including a control store for storing computer program indicia for sensing same and responding to the sensed indicia to send out the control signals and to sense and analyse the received command and status signals; the stores each having addressable data storing tracks of equal data-storage capacity; means in the programmed control stored computer program indicia to cause the programmed control to allocate predetermined ones of the cache tracks to store data addressably stored for predetermined respective ones of the backing store tracks; and means in the cache store for addressing the allocated cache tracks using the addresses of the predetermined respective ones of the tracks in the backing store: monitoring program indicia in the control store for being sensed by the programmed control for executing computer programming contained in such indicia for causing the programmed control for operating the system to monitor the data transfers between the attachment means and the cache store addressed ones of the allocated cache tracks for measuring the length of data in each such transfer and storing the measured data lengths, then summing the measured data lengths for all data transfers between the attachment means and the respective cache tracks to create a stored access extent for each of the cache tracks allocated to store data; threshold indicia in the control store for indicating a threshold value and being sensible by the programmed control for obtaining the threshold value; indicator means in the data transfer means for indicating a completion of a last data transfer between the cache store and the attachment means and the backing store address for the cache track used in the data transfer; comparison program indicia in the control store for being sensed by the programmed control for executing computer programming contained is such indicia causing the programmed control to operate the system for sensing the completion indicator and responding thereto sensing the stored access extents for the cache track used in the last data transfer and for "K" cache tracks respectively addressable by backing store addresses contiguous with the backing store address for the last access cache track, then the programmed control processing the sensed stored access extents using predetermined calculations to create an intermediate value is greater than the threshold value, indicating a sequential mode of operation for data transfers in the last accessed cache track, wherein "K" is an integer; and data promotion program indicia in the control store for being sensed by the programmed control for executing computer programming contained in such indicia for causing the programmed control to operate the system for sensing the sequential indicator, if the sequential indicator is set, then causing the programmed control to operate the system for promoting data from next backing store tracks to cache store tracks with the tracks having backing store address contiguous with and greater than the backing store address of the last accessed cache track, calculating the number of tracks to be promoted by sensing the intermediate value and changing the intermediate value by predetermined calculations, then activating the data transfer means for promoting the data stored in the next backing store tracks.

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