Digitally adjustable and calibrated delay line and method

Claim 2

A delay line comprising: a plurality of cells, each said cell having a cell input and cell output terminal; a CMOS transistor comprising a first PMOS/NMOS pair of transistors, said PMOS/NMOS transistors each having a gate, source and drain electrode wherein said drain electrode of said first NMOS transistor is connected to said drain electrode of said first PMOS transistor and to said cell output terminal, and wherein said gate electrode of said first PMOS transistor and said gate electrode of said first NMOS transistor are connected to said cell input terminal; a plurality of second PMOS transistors, each having source, drain and gate electrodes; said first PMOS transistor having its said source electrode connected to said drain electrodes of each of said second PMOS transistors; a plurality of second NMOS transistors, each having source, drain and gate electrodes; said first NMOS transistor having its said source electrode connected to said drain electrode of each of said second NMOS transistors; each said drain electrode of each said second PMOS transistor being adapted for connection to a positive bias potential; each said drain electrode of each said second NMOS transistor being adapted for connection to a ground potential; a first control terminal adapted for receiving a first control voltage; a second control terminal adapted for receiving a second control voltage; a means for switchably connecting said first and second control terminals to a first and second group of selected gate electrodes respectively of said second PMOS and said second NMOS transistors, said gate electrodes in each said first and second groups selected to provide a desired propagation delay on said delay line; said plurality of cells being connected together with said cell output terminal of each one of said cells being connected to said cell input terminal of a next one of said cells beginning with a first one of said cells having its cell input terminal adapted as a delay line input for connection to a signal source and a last one of said cells having a cell output terminal adapted as a delay line output terminal.

Claim 3

A delay line as in claim 1 further comprising a plurality of sampling buffers, one buffer for a predetermined one of said cells respectively, each said buffer having a clocking terminal and a sampling terminal, said sampling terminal being connected to a said cell output terminal of a said predetermined one of said cells.

Claim 4

A delay line as in claim 2 which includes a plurality of sampling buffers, one buffer for a preselected one of said cells respectively, each said buffer having a clocking terminal and a sampling terminal, said sampling terminal being connected to said cell output terminal of said preselected cell.

Claim 5

A delay line as in claim 3 wherein said sampling buffer comprises: a D flipflop having a flipflop input terminal, a clock terminal and a flipflop output terminal; said clock terminal being connected to said delay line input terminal; and said flipflop input terminal being said buffer sampling terminal whereby a signal is elicited on said flipflop output terminal corresponding to the signal at said sampling terminal clocked by said input to said delay line.

Claim 6

A delay line as in claim 4 wherein said buffer comprises: a D flipflop having a flipflop input terminal, a clock terminal and a flipflop output terminal; said clock terminal being connected to said delay line input terminal; said flipflop input terminal being connected to one of said selected sampling terminals respectively whereby a signal is elicted on said flipflop output terminal responsive to a signal at said sampling terminal clocked by a delay line input signal.

Claim 7

A delay line as in claim 5 wherein means for detecting the position of said pulse edge includes: a plurality of NAND gates, each said NAND gate having two input terminals; one terminal of each NAND gate being connected to an input terminal of a neighboring NAND gate and to an output terminal of one of said D flipflops, respectively, such that when a transition edge of a propagated signal exists between two neighboring selected sampling points, a logical one will be elicited by said output terminal of said NAND gate having its inputs connected to said D flipflops having flipflop terminals connected to said neighboring sampling points on both sides of said transition of said pulse edge.

Claim 8

A delay line as in claim 6 wherein means for detecting position of said pulse edge includes: a plurality of NAND gates, each said NAND gate having two input terminals; one terminal of each NAND gate being connected to an input terminal of a neighboring NAND gate and to an output terminal of one of said D flipflops, respectively, such that when a transition edge of a propagated signal exists between two neighboring selected sampling points, a logical one signal will be elicited by said output terminal of said NAND gate having its inputs connected to said D flipflops having flipflop input terminals connected to said neighboring sampling points on both sides of said transition of said pulse edge.

Claim 9

The delay line of claim 2 wherein said means for switchably connecting includes, one FET switch member for each PMOS/NMOS transistor pair, each said FET switch member having a gate, source and drain, said source electrodes of said FET switch member being connected to said gate electrode of said respective second NMOS transistor; a plurality of control inverters, one said control inverter for each said second PMOS/NMOS transistor pair, each control inverter having a first inverter terminal connected to said FET source and a second control inverter terminal connected to a gate electrode of said respective second PMOS transistor of said PMOS/NMOS transistor pair.

Claim 10

A delay line as in claim 9 further comprising an OR gate corresponding to each FET switch, said OR having one output and a pair of inputs; each said gate of said FET switch member is coupled to said output of said OR gate.

Claim 11

The delay line of claim 8 wherein said means for switchably connecting includes a plurality of FET switch members, one FET switch member for each second PMOS/NMOS transistor pair, each said FET switch member having a gate terminal and a first and second channel terminals, said first channel terminal being connected to said gate electrode of said respective second NMOS transistor.

Claim 12

The delay line of claim 1 further comprising on algorithmic state machine connected to said means for controlling and calibrating said delay line; and wherein said first portion of said means for controlling comprising a plurality of parallel PMOS transistors

Claim 13

The delay line of claim 12 wherein said algorithmic state machine includes a coarse and fine select register; a sequence state machine controller; said sequence state machine controller coupled to said course and fine registers; and said coarse and fine register, responsive to said sequence state machine controller, provides control signals to said means for controlling and calibrating said delay line.

Claim 14

A delay line as in claim 13 including a plurality of OR gates, each said OR gate including two OR input terminals and an OR output terminal, said OR output terminal being coupled to a said gate electrode of a said PMOS transistor; wherein said delay line further comprises, each said coarse and fine register having a plurality of register output terminals, one register output terminal connected to one OR input terminal respectively for applying a digital code signal to said OR input terminals; a plurality of sampling terminals connected between groups of said cells; and a plurality of AND gates, each said AND gate having an output terminal and a plurality of AND input terminals, each AND input terminal being coupled to two of said sampling terminals such that a logic one signal is elicited on said AND output terminal when a transition edge from a propagated signal exists in the delay line between said sampling terminals.

Claim 16

A method as in claim 15 wherein, step (a), includes adjusting said propagation delay of said selected cells such that an edge transition of a propagating signal occurs at a sampling terminal distant from said output terminal; and wherein said step (b) includes adjusting propagation delays simultaneously of groups of said cells such as to effect coarse movements of said transition toward said output terminal of said delay line, and then adjusting propagation delays of selected single cells such as to effect fine movement of said transition toward said output terminal of said delay line.

Claim 17

The method of claim 16 wherein both step (a) and step (b) are controlled by a sequence controller according to a algorithm.

Claim 18

The method of claim 17 wherein said algorithm attempts to maintain said transition in a target position between two said selected cells of said delay line and so long as said transition is within a predetermined number of said cells from its said target position, said algorithms will cause said sequence controller to remain in said fine movement mode of step (b).