Signal delay method, signal delay device and circuit for use in the apparatus

Claim 3

The method of claim 2, wherein said detected delayed signal has a predetermined phase difference with respect to said input signal.

Claim 4

A circuit for using in providing a delayed signal, comprising: (a) means for delaying an input signal to produce a plurality of delayed signals having different delay times from each other with respect to said input signal; and (b) means for detecting a delayed signal having a specific relation with said input signal from said plurality of delayed signals, wherein said delaying means and said detecting means are conducted in a single integrated circuit unit.

Claim 6

The device of claim 5, wherein said desired delayed signal is selected according to a property of said input signal which substantially does not change according to outer factors.

Claim 8

The device of claim 7, wherein said detecting means detects a delayed signal having a predetermined phase relation with said input signal.

Claim 12

The device of claim 7, wherein said detecting means comprises a plurality of phase detecting means for detecting a plurality of specific delayed signals having specific relations with said input signal from said plurality of delayed signals, and further comprising masking means for making only one of said phase detecting means operative.

Claim 13

The device of claim 12, wherein said one of said phase detecting means detects the specific delayed signal having a shortest delay time.

Claim 14

The device of claim 13, wherein said plurality of phase detecting means are divided into a plurality of groups, one of said plurality of specific delayed signals is detected in each of said groups, and said masking means output signals for inhibiting said specific delayed signal from being detected in other groups when said specific delayed signal is detected in one of said groups.

Claim 15

The device of claim 8, wherein said determining means outputs a delayed signal having a longest delay time to said input signal when said detecting means detects no delayed signal.

Claim 16

The device of claim 8, wherein said detecting means detects a delayed signal having the same phase as or phase reverse to that of said input signal.

Claim 17

The device of claim 8, wherein said determining means designates a delayed signal output from a point corresponding to A satisfying the following equation as said desired signal to be output: A = (B/C) × D - E/F where A represents either the number of circuit elements exist from a point where the input signal is input into a point on said delaying means where a delayed signal corresponding to said desired delayed signal is output, or a path length from a point where the input signal is input into a point on said delaying means where a delayed signal corresponding to said desired delayed signal is output; B represents a desired delayed time; C represents either one period of the input signal when said detecting means detects a delayed signal having the same phase as that of the input signal, or a half period of the input signal when said detecting means detects a delayed signal having phase reverse to the input signal; D represents either the number of circuit elements which exist from a point where the input signal is input into a point on said delaying means where a delayed signal corresponding to said detected signal is obtained, or a path length from a point where the input signal is input into a point on said delaying means where a delayed signal corresponding to said detected signals obtained; E represents a delayed time which is obtained by subtracting a delay time required for a passage of the input signal through said delaying means from entire delayed time required for a passage of the input signal through a signal path from a point where the input signal is input into a point where said delayed signal is output; and F represents a standard delay time required for a passage of the input signal through unit circuit elements or unit path length.

Claim 18

The device of claim 8, wherein said determining means comprises a plurality of determining units, each of said plurality of determining units determines a desired delayed signal to be output from said plurality of delayed signals according to the detected result by said detecting means.

Claim 19

The device of claim 8 further comprising control means for determining wherein said control means is controllable if said desired delayed signal from said determining means is output.

Claim 20

The device of claim 8, wherein at least said delaying means and said determining means are provided in a single integrated circuit unit together with other circuit into which said desired delayed signal output from said determining means is input.

Claim 21

The device of claim 20, wherein said other circuit comprises a pulse width modulating circuit.

Claim 22

The device of claim 20, wherein said other circuit comprises a synchronizing circuit.

Claim 23

The device of claim 8, wherein said input signal is a clock signal being a rectangular wave.

Claim 24

The device of claim 16, wherein said input signal is a clock signal being a rectangular wave.

Claim 25

The device of claim 8, wherein said delaying means comprises a plurality of circuit elements connected in series in which said plurality of delayed signals are output between said plurality of circuit elements.

Claim 26

A circuit for providing a desired delayed signal, comprising: (a) signal delaying means having a plurality of circuit elements connected in series, a clock signal having rectangular wave form being input into a terminal of said circuit elements, for outputting a plurality of delayed signals, each delayed signal having different delay time from said clock signal from positions between said plurality of circuit elements; (b) means for detecting a delayed signal having either the same phase or the reverse phase with respect to said clock signal from said plurality of delayed signals; and (c) means for determining a delayed signal output from a point corresponding to A satisfying the following equation as said desired delayed signal to be output, and at least said delaying means and said determining means are provided in a single integrated circuit unit; A = (B/C) × D - E/F where A represents the number of circuit elements where exist from a point where the clock signal is input into a point on said delaying means where a delayed signal corresponding to said desired delayed signal is output; B represents a desired delay time; C represents either one period of the clock signal when said detecting means detects a delayed signal having the same phase as that of the clock signal, or a half period of the clock signal when said detecting means detects a delayed signal having phase reverse to that of the clock signal; D represents the number of circuit elements where exist from a point on said delaying means where a delayed signal corresponding to said detected signal is obtained; E represents a delayed time which is obtained by subtracting a delay time for a passage of the clock signal through said delaying means from entire delayed time required for a passage of the clock signal through a signal path from a point where the clock signal is input into a point where said delayed signal is output; and F represents a standard delay time required for a passage of the clock signal through unit circuit elements.