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US4939677A Expired / Lapsed US ⏱️ 0.0 years remaining

Timing-signal delay equipment

Assignee: NTT Inc
•
Filing: 1987-10-02
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Granted: 1990-07-03
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Expires: 2007-10-02
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Abstract

Abstract Timing-signal delay equipment which provides an adjustable delay time, equal to a multiple of a predetermined time unit, to an input signal pulse is used as a timing source required in a circuit tester of LSIs (semiconductor large-scale integrated circuits). The timing-signal delay equipment has a plurality of delay elements (D ij 's) with weighted delay times arranged in a matrix form; a selector (S) coupled with the matrix for selecting one of the delay elements for each column of the matrix, wherein the selected delay elements are connected in series; and an arithmetic control circuit (M) that controls the selectors based on a set-up value of delay time and an error in delay time of each delay equipment. In order to provide a delay time which is equal to a multiple of a predetermined time unit in spite of an error in delay time of each delay element, either a correction matrix is connected in series to the matrix or the weight of each delay element is modified.

Inventors

  • 👤 Taiichi Otuji
  • 👤 Naoaki Narumi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 23:36
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/14; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; H03K5/131; H03K5/133; H03K5/15; H03K2005/00013; H03K2005/00019; H03K2005/00026; H03K2005/00045; H03K2005/0015; H03K2005/00234; H03K2005/00267; H03K2005/0028

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 129 words
Timing-signal delay equipment, comprising; a plurality of delay elements arranged in a matrix form, each of which gives a mutually different value of weighted delay time to an input signal; a selector means operably connected to each matrix column for selecting one of said delay elements; a means for connecting said selected delay elements in series; an arithmetic control circuit means for controlling said selector means based on a set-up value delay time and an error lay time of each delay element, wherein delay time T ij of said ay element satisfies following equation: T.sub.ij =T.sub.d (i-1)m.sup.j-1 where T d is set-up temporal resolution; i is row number of the delay element; j is column number of the delay element; and m is column number of rows in matrix.
Claim 2
Dependent Claim 129 words
Timing-signal delay equipment, comprising; a plurality of delay elements arranged in a matrix form, each of which gives a mutually different value of weighted delay time to an input signal; a selector means operably connected to each matrix column for selecting one of said delay elements; a means for connecting said selected delay elements in series; an arithmetic control circuit means for controlling said selector means based on a set-up value delay time and an error lay time of each delay element, wherein delay time T ij of said ay element satisfies following equation: T.sub.ij =T.sub.d (i-1)m.sup.j-1 where T d is set-up temporal resolution; i is row number of the delay element; j is column number of the delay element; and m is column number of rows in matrix.
Claim 3
Dependent Claim 113 words
Timing-signal delay equipment according to claim 1, wherein at least one correction matrix delay circuit device is provided, in series with said timing-signal delay equipment, said correction matrix delay circuit device having a plural number of weighted delay elements arranged in a matrix form, a selector for selecting one of its delay elements for each column of said matrix by the control of said arithmetic control circuit, and a means to connect selected delay circuits in series, so that a delay time being equal to a multiple of the set-up temporal resolution T d is obtained although each delay element has an error in its delay time by means of said correction matrix.
Claim 4
Dependent Claim 60 words
Timing-signal delay equipment according to claim 2, wherein the following relation is satisfied by the delay time T.sub.αβ of any delay element in said correction matrix. T.sub.αβ =T.sub.d (α-1)K.sup.β-1 where α is row number of the delay element in correction matrix; β is column number of the delay element in correction matrix; K is number of rows in correction matrix.
Claim 5
Dependent Claim 11 words
Timing-signal delay equipment according to claim (1), wherein m≧3 is satisfied.
Claim 6
Dependent Claim 146 words
Timing-signal delay equipment, comprising: a plurality of delay elements arranged in a matrix form, each of which gives a mutually different value of weighted delay time to an input signal; a selector means operably connected to each matrix column for selecting one of said delay elements; a means for connecting said selected delay elements in series; and an arithmetic control circuit means for controlling said selector means based on a set-up value of delay time and an error in delay time based on each delay element, wherein delay time T ij of said delay element satisfies following equation: ##EQU3## where T d is set-up temporal resolution; i is row number of the delay element; j is column number of the delay element; m is number of rows in matrix; and e is absolute value of a relative error rate in delay time of each delay element.
Claim 7
Dependent Claim 146 words
Timing-signal delay equipment, comprising: a plurality of delay elements arranged in a matrix form, each of which gives a mutually different value of weighted delay time to an input signal; a selector means operably connected to each matrix column for selecting one of said delay elements; a means for connecting said selected delay elements in series; and an arithmetic control circuit means for controlling said selector means based on a set-up value of delay time and an error in delay time based on each delay element, wherein delay time T ij of said delay element satisfies following equation: ##EQU3## where T d is set-up temporal resolution; i is row number of the delay element; j is column number of the delay element; m is number of rows in matrix; and e is absolute value of a relative error rate in delay time of each delay element.
Claim 8
Dependent Claim 139 words
Timing-signal delay equipment, comprising: a plurality of delay elements arranged in a matrix form, each of which gives a mutually different value of weighted delay time to an input signal; a selector means operably connected to each matrix column for selecting one of said delay elements; a means for connecting said selected delay elements in series and arranged in matrix rows; and an arithmetic control circuit means for controlling said selector means based on a set-up value of delay time and an error in delay time of each delay element, wherein delay time of each delay element is identified by matrix rows and columns, and is a function of an expected set-up temporal resolution and a function of a number of said matrix rows to thereby provide an output timing signal having a delay time of a precise value.
Claim 9
Dependent Claim 139 words
Timing-signal delay equipment, comprising: a plurality of delay elements arranged in a matrix form, each of which gives a mutually different value of weighted delay time to an input signal; a selector means operably connected to each matrix column for selecting one of said delay elements; a means for connecting said selected delay elements in series and arranged in matrix rows; and an arithmetic control circuit means for controlling said selector means based on a set-up value of delay time and an error in delay time of each delay element, wherein delay time of each delay element is identified by matrix rows and columns, and is a function of an expected set-up temporal resolution and a function of a number of said matrix rows to thereby provide an output timing signal having a delay time of a precise value.

References Cited (Backward Citations)

US3763317A Cited
JPS5538710A Cited
US4287437A Cited
US4541100A Cited
US4497056A Cited
US4495628A Cited
US4656632A Cited
US4637733A Cited
US4775954A Cited
US4701920A Cited
US4672307A Cited
US4783606A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-07-02 1994-01-01 1994-07-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-07-02 1998-01-01 1998-07-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-07-02 2002-01-01 2002-07-03 $7700.00 Window Closed / Lapsed

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