EP0508156A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Copper alloy metallurgies for VLSI interconnection structures
Assignee: International Business Machines Corp
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Filing: 1992-03-14
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Granted: —
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Expires: 2012-03-14
Abstract
Abstract A method for providing vias, lines and other recesses in VLSI interconnection structures (28) with copper alloys to create a thin layer (32) of an oxide of an alloying element on the surface of the deposited alloy and on portions of the alloy which are in contact with an oxygen containing dielectric (16) is disclosed. The present invention is also directed to VLSI interconnection structures which utilize this copper alloy and thin oxide layer (32) in their vias, lines and other recesses. The oxide layer (32) eliminates the need for diffusion barrier and/or adhesion layers and provides corrosion resistance for the deposited copper alloy. VLSI devices utilizing this copper alloy in the vias, lines and other recesses interconnecting semiconductor regions, devices and conductive layers on the VLSI device are significantly improved.
Inventors
- 👤 James Mckell Edwin Harper
- 👤 Karen Lynne Holloway
- 👤 Thomas Yu-Kiu Kwok
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 12:22
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/077; H10W20/031; H10W20/056; H10W20/057; H10W20/064; H10W20/065; H10W20/076; H10W20/40; H10W20/41; H10W20/425; H10W20/44; H10W20/4403; H10W20/4421; H10W20/4424
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
106 words
A method of forming a copper alloy conductive plug in a recess in a VLSI interconnection structure defined in an oxygen containing dielectric layer (16) disposed on one main planar surface of a substrate comprising the steps of: (a) providing a copper alloy of copper and an alloying element of less than 2.0 atomic percent; (b) depositing said copper alloy into the recess of the interconnection structure and forming a copper alloy plug and a thin layer of an oxide of the alloying element on an exposed surface of said plug and on surfaces of said plug which are in contact with said oxygen containing dielectric.
Claim 2
Dependent Claim
33 words
The method of claim 1, wherein said depositing step comprises depositing said copper alloy at a deposition temperature such that said thin oxide layer forms simultaneously with the deposition of said copper alloy.
Claim 3
Dependent Claim
17 words
The method of claim 2, wherein said deposition temperature is in the range of 150°C to 250°C.
Claim 4
Dependent Claim
34 words
The method of claim 1, wherein said depositing step comprises: (a) depositing said copper alloy into the recess of the interconnection structure; and (b) annealing said interconnection structure to form said thin oxide layer.
Claim 5
Dependent Claim
24 words
The method of claim 4, wherein said annealing step comprises annealing said interconnection structure at a temperature in the range of 250°C to 400°C.
Claim 6
Independent Claim
28 words
The method of any one of the preceding claims, wherein said oxygen containing dielectric layer comprises a dielectric selected from the group consisting of silicon dioxide and polyimide.
Claim 7
Independent Claim
25 words
The method of any one of the preceding claims, wherein said alloying element comprises an element selected from the group consisting of chromium and aluminum.
Claim 8
Independent Claim
28 words
The method of any one of the preceding claims, wherein said thin oxide layer comprises an oxide selected from the group consisting of chromium oxide and aluminum oxide.
Claim 9
Independent Claim
14 words
The method of any one of the preceding claims, wherein said substrate comprises copper.
Claim 10
Independent Claim
70 words
The method of any one of the preceding claims, wherein said substrate further comprises: a refractory metal barrier layer formed at the bottom of the recess and in contact with a bottom surface of said plug and a portion of an upper surface of said substrate; and a metal silicide layer formed in an upper portion of said substrate and in contact with a bottom surface of said barrier layer.
Claim 11
Dependent Claim
10 words
The method of claim 10, wherein said substrate comprises silicon.
Claim 12
Dependent Claim
94 words
A VLSI interconnection structure comprising: a substrate (12) having at least one oxygen containing dielectric layer (16) formed on one main planar surface of said substrate; and a conductive plug (30,42,50) formed in a recess (14) defined in said oxygen containing dielectric, said conductive plug comprising a copper alloy of copper and an alloying element of less than 2.0 atomic percent, and a layer of an oxide of said alloying element formed on an exposed surface of said copper alloy and on surfaces of said copper alloy in contact with said oxygen containing dielectric.
Claim 13
Dependent Claim
68 words
The structure of claim 12, wherein said substrate further comprises: a refractory metal barrier layer (24) formed at the bottom of the recess and in contact with a bottom surface of said plug (50) and a portion of an upper surface of said substrate; and a metal silicide layer formed in an upper portion of said substrate and in contact with a bottom surface of said barrier layer.
References Cited (Backward Citations)
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