Patent EP0458293A1 successfully refreshed from Google Patents.
EP0458293A1
Expired / Lapsed
EP
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Multilayer wiring board and method for manufacturing the same
Assignee: Sony Corp
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Filing: 1991-05-22
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Granted: —
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Expires: 2011-05-22
Abstract
Abstract A multilayer wiring board and a method for manufacturing the same are disclosed. The wiring board comprises an insulating substrate (1) having a first (3) and second conductor layers (4) formed on major surfaces of the insulating substrate, a blind hole (6) formed through the first conductor layer (3) and the insulating substrate (1) to expose the second conductor layer (4) at the bottom of the blind hole (6), and a connecting conductor (7) provided to cover the exposed surface of the second conductor layer (4) wall portion of the blind hole and the first conductor layer (3). Since the connecting conductor (7) and the second conductor (4) are made in surface contact, connection reliability is very much improved. The blind hole (6) is made by blasting a fine abrasive powder beam to selectively remove the insulating substrate (1). The end of selective removal can be easily controlled by the difference of working speed against the insulating substrate and the conductor layer to successfully expose the second conductor layer at the bottom of the blind hole.
Inventors
- 👤 Nobuyuki Yasuda
- 👤 Toshio Tamura
- 👤 Hiroshi Toi
- 👤 Akio Mishima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 21:26
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/0011; H05K3/0044; H05K1/00; H05K1/02; H05K1/11; H05K1/115; H05K3/46; H05K3/4644; H05K3/4652; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0355; H05K2201/0388; H05K2201/0394; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09509; H05K2201/09518; H05K2201/09654; H05K2201/09809; H05K2201/09818; H05K2201/09845; H05K2203/00; H05K2203/02; H05K2203/025; H05K2203/05; H05K2203/0548; H05K2203/0554; H05K3/40; H05K3/42; H05K3/429; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49165
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
118 words
A multilayer wiring board comprising; a) an insulating substrate (1) having a first and a second major surfaces, b) a first conductor layer (3) formed on said first major surface of said substrate, c) a second conductor layer (4) formed on said second major surface of said substrate. d) a hole portion (6) extending from said first conductor layer through said insulating substrate to said second conductor layer exposing said second conductor layer at a bottom of said hole portion, and e) a third conductor layer (7) formed to cover said first conductor layer (3), a side wall surface of said hole portion (6), and said second conductor layer (4) exposed at said bottom of said hole portion.
Claim 2
Dependent Claim
29 words
A multilayer wiring board according to claim 1, a plurality of fine hole portions and third conductor layers are provided to electrically connect said first and second conductor layers.
Claim 3
Dependent Claim
236 words
A multilayer wiring board comprising; a) a first insulating layer, b) a second insulating layer, c) a first conductor layer formed on a major surface of said first insulating layer, d) a second conductor layer formed between said first and said second insulating layer and on opposite surface of said first insulating layer to said first conductor layer, e) a third conductor layer formed on a major surface of said second insulating layer opposite to said second conductor layer, f) a first hole portion having a first size of opening extending from said first conductor layer through said first insulating layer to said second conductor layer exposing said second conductor layer at a bottom of said first hole portion, g) a second hole portion having a second size of opening smaller than said first size of opening provided at a position where said first hole portion is provided and extending from said second conductor layer through said second insulating layer to said third conductor layer exposing said third conductor layer at a bottom of said second hole portion, and h) a fourth conductor layer formed to cover said first conductor layer, a side wall surface of said first hole portion, said second conductor layer exposed at said bottom of said first hole portion, a side wall surface of said second hole portion and said third conductor layer exposed at said bottom of said second hole portion.
Claim 4
Dependent Claim
171 words
A multilayer wiring board comprising; a) a first insulating layer b) a second insulating layer, c) a first conductor layer formed on a major surface of said first insulating layer, d) a second conductor layer formed between said first and second insulating layer and on opposite surface of said first insulating layer to said first conductor layer, said second conductor having an opening having a first size, e) a third conductor layer formed on a major surface opposite to said second conductor layer, f) a hole portion having a second size smaller than said first size extending from said first conductor layer through said first insulating layer, said opening formed in said second conductor layer and said second insulating layer to said third conductor layer exposing said third conductor layer at a bottom of said hole portion, and g) a fourth conductor layer formed to cover said first conductor layer, a side wall surface of said hole portion, and said third conductor layer exposed at said bottom of said hole portion.
Claim 5
Dependent Claim
23 words
A multilayer wiring board according to claim 1, said second conductor layer having an opening having a smaller size than said hole portion.
Claim 6
Independent Claim
112 words
A method for manufacturing a multilayer wiring board comprising the steps of; a) forming a first conductor layer on a second major surface of an insulating substrate, b) forming a patterned mask which is resistant to the subsequent etching on a first major surface of said insulating substrate, c) blasting a fine abrasive powder from the side of said first major surface to selectively remove said insulating substrate until said first conductor layer is exposed at a bottom of a hole portion thus formed, and d) forming a second conductor layer to cover side wall surface of said hole portion and said first conductor exposed at said bottom of said hole portion.
Claim 7
Dependent Claim
25 words
A method according to claim 6, wherein said patterned mask is a third conductor layer formed on said first major surface of said insulating substrate.
Claim 8
Dependent Claim
37 words
A method according to claim 6, wherein said patterned mask is a third conductor layer formed on said first major surface of said insulating layer and an elastic resinous material layer formed on said third conductor layer.
Claim 9
Dependent Claim
20 words
A method according to claim 6, wherein said fine abrasive powder has an average powder diameter not exceeding 16 µm.
Claim 10
Dependent Claim
21 words
A method according to claim 6, wherein said fine abrasive powder has hardness larger than a hardness of said insulating substrate.
References Cited (Backward Citations)
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