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EP0447577A1
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High-performance computer system with fault-tolerant capability
Assignee: Tandem Computers Inc
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Filing: 1990-03-19
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Granted: —
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Expires: 2010-03-19
Abstract
Abstract A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.
Inventors
- 👤 Richard W. Cutts Jr.
- 👤 Randall G. Banton
- 👤 Douglas E. Jewett
- 👤 Peter C. Norwood
- 👤 Kenneth C. Debacker
- 👤 Nikhil A. Mehta
- 👤 John David Allison
- 👤 Robert W. Horst
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 10:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/16; G06F11/1629; G06F11/1641; G06F11/1658; G06F11/1666; G06F11/1675; G06F11/1683; G06F11/1687; G06F11/1691; G06F11/18; G06F11/183; G06F11/184; G06F11/185; G06F11/20; G06F11/2017; G06F9/3824; G06F9/3836; G06F9/3851; G06F9/3885; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/08; G06F11/10; G06F11/1008; G06F11/14; G06F11/1402; G06F11/1405; G06F11/1415; G06F11/1679; G06F11/181; G06F11/182; G06F11/2015; G06F2201/00; G06F2201/85; G11; G11C; G11C29/00; G11C29/70; G11C29/74
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
138 words
A fault-tolerant computer system, comprising: a) first, second and third CPUs of substantially identical configuration, said first, second and third CPUs executing substantially the same instruction stream; b) first and second memory modules of substantially identical configuration, said first and second memory modules storing substantially the same data; c) busses coupling each of the first, second and third CPUs individually to each of said first and second memory modules whereby said first, second and third CPUs access said first and second memory modules separately and in duplicate; d) a first input/output bus coupled to said first memory module and a second input/output bus coupled to said second memory module; and e) a first input/output processor coupled to both said first and second input/output busses, and a second input/output processor coupled to both said first and second input/output busses.
Claim 2
Dependent Claim
23 words
A system according to claim 1 wherein said first, second and third CPUs are loosely synchronized upon the event of a memory reference.
Claim 3
Dependent Claim
65 words
A system according to claim 2 wherein said first, second and third CPUs are loosely synchronized upon the event of a memory reference by detecting an access by said CPUs to said first and second memory modules and stalling any CPUs for which the access occurs earlier to wait until the last one of said CPUs executes said access, then allowing the access to occur.
Claim 4
Dependent Claim
24 words
A system according to claim 1 wherein said first, second and third CPUs are operating on independent clocks so that said execution is asynchronous.
Claim 5
Dependent Claim
79 words
A system according to claim 1 wherein either of said memory modules is designated as a primary memory and the other is designated as back-up, and wherein write operations by the CPUs are executed in both of said memory modules but in read operations said CPUs receive data from only the primary memory module; and wherein the back-up memory module may be designated as the primary memory and the primary may be designated as the back-up, at any time.
Claim 6
Dependent Claim
22 words
A system according to claim 1 including at least one additional input/output processor connected to both said first and second input/output busses.
Claim 7
Dependent Claim
47 words
A system according to claim 1 wherein said memory modules include means for voting said memory references, and wherein data is voted only for memory writes in said means for voting said memory references, and addresses and commands are voted for both memory reads and memory writes.
Claim 8
Dependent Claim
33 words
A system according to claim 7 wherein each of said memory modules includes a random access memory and said random access memory is accessed in parallel with operation of said means for voting.
Claim 9
Dependent Claim
32 words
A system according to claim 1 wherein when one of said first, second and third CPUs fails, said one is placed off-line and the remaining two continue to execute said instruction stream.
Claim 10
Independent Claim
94 words
A method of operating a redundant computer system, comprising the steps of: a) executing the same instruction stream in each of first, second and third individually-clocked CPUs; b) storing identical data in first and second memory modules; c) executing memory references by each of the first, second and third CPUs individually to each of said first and second memory modules; and d) performing store or recall operations in said first and second memory modules in response to said memory references when said memory references have been received from said first, second and third CPUs.
Claim 11
Dependent Claim
73 words
A method according to claim 10 including the steps of: e) executing input/output functions separately to a first input/output bus coupled to said first memory module and to a second input/output bus coupled to said second memory module; and f) processing said input/output functions in a first input/output processor connected to both said first and second input/output busses, and in a second input/output processor connected to both said first and second input/output busses.
Claim 12
Dependent Claim
48 words
A method according to claim 11 including the step of loosely synchronizing said first, second and third CPUs by detecting synchronization upon the event of a memory reference and stalling any one of the CPUs leading another CPU so the event is executed by all three in synchronization.
Claim 13
Dependent Claim
30 words
A method according to claim 10 including the step of processing said input/output functions in at least one additional input/output processor connected to both said first and second input/output busses.
Claim 14
Dependent Claim
26 words
A method according to claim 11 including the step of voting said memory references and thereby synchronizing said first, second and third CPUs with one another.
Claim 15
Dependent Claim
72 words
A method according to claim 10 including the step of voting said memory accesses to both said first and second memory modules from said first, second and third CPUs; and including the step of accessing the memory of said each said first and second memory modules while at the same time performing said step of voting so that when the step of voting is completed the memory access can be immediately validated.
Claim 16
Dependent Claim
117 words
A computer system comprising: a) first, second and third CPUs executing the same instruction stream, each of said CPUs having a separate memory access port; b) first and second memory means having identical address spaces within the address range of said CPUs for storing duplicative data, each one of said first and second memory means having first, second and third input/output ports coupled to said memory access ports of said first, second and third CPUs, respectively; c) each one of said first, second and third ports including voting means to compare information between the ports for accesses and to allow accesses to be completed only where at least two of the ports have the same such information.
Claim 17
Dependent Claim
49 words
A computer system according to claim 16 including first and second input/output busses, and wherein said first and second memory means each has a separate peripheral I/O port, and said first and second input/output busses are separately coupled to said I/O ports of said first and second memory means.
Claim 18
Dependent Claim
43 words
A computer system according to claim 16 including means for synchronizing execution of the instruction stream in said CPUs by stalling execution of a memory reference until all three of said first, second and third CPUs are executing the exact same memory reference.
Claim 19
Dependent Claim
17 words
A system according to claim 16 wherein said information includes address and data information for write operations.
Claim 20
Dependent Claim
45 words
A system according to claim 16 wherein each one of said CPUs has a separate clock whereby said CPUs operate asynchronously, and wherein each one of said first and second memory modules has a separate clock, whereby said CPUs and memory modules all operate asynchronously.
Claim 21
Dependent Claim
33 words
A system according to claim 20 wherein said CPUs are loosely synchronized with one another by stalling leading CPUs until the slower CPUs have caught up, upon the event of a memory reference.
Claim 22
Independent Claim
146 words
A method of operating a computer system comprising the steps of: a) executing the same instruction stream in first, second and third CPUs; b) generating memory accesses in each of said first, second and third CPUs at separate first, second and third memory access busses; c) storing duplicative data in first and second memory means having substantially identical address spaces within the address range of said CPUs, including executing memory accesses to each one of said first and second memory means via said first, second and third memory busses; d) voting each one of said memory accesses in said first and second memory means when received from said first, second and third memory access busses, said voting including comparing information representing said memory accesses; and (e) allowing said accesses to be completed only where at least two of said access busses present the same such information
Claim 23
Dependent Claim
62 words
A method according to claim 22 including the step of synchronizing said first, second and third CPUs whereby said CPUs are substantially simultaneously executing the same instruction stream, and wherein said step of synchronizing said CPUs includes stalling execution of memory accesses until all three of the first, second and third CPUs is executing the same memory access at the same time.
Claim 24
Dependent Claim
45 words
A method according to claim 23 wherein said step of synchronizing also includes timing the implementation of external interrupts of the CPUs so that all three of the first, second and third CPUs are executing the same instruction at the time the interrupt is presented.
Claim 25
Independent Claim
88 words
A method of operating a computer system comprising the steps of: a) executing the same instruction stream in at least first and second processors; b) generating remote accesses in each of said first and second processors, the remote accesses being directed to separate first and second access ports; c) detecting each one of said remote accesses at said first and second access ports and stalling executing of instructions in said first and second processors until a remote access is detected at both the first and second access ports.
Claim 26
Dependent Claim
34 words
A method according to claim 25 wherein said step of executing is in first, second and third processors, and wherein said step of generating remote accesses is in said first, second and third processors.
Claim 27
Dependent Claim
37 words
A method according to claim 26 wherein said first and second access ports are in first and second modules operated asynchronous to said first, second and third processors; and wherein said first and second processors are asynchronous.
Claim 28
Dependent Claim
45 words
A method according to claim 25 including the step of storing duplicative data in first and second address spaces within the address range of said processors, and executing accesses to each one of said first and second address spaces via first and second access busses.
Claim 29
Dependent Claim
35 words
A method according to claim 25 including the step of synchronizing any interrupts executed by said first and second processors whereby said processors execute the same interrupt at the same instruction in said instruction stream.
Claim 30
Dependent Claim
39 words
A method according to claim 29 wherein said step of synchronizing said processors includes stalling execution of memory accesses until all three of the first, second and third processors are executing the same memory access at the same time.
Claim 31
Dependent Claim
39 words
A method according to claim 29 wherein said step of synchronizing also includes stalling execution of interrupts of the CPUs until all three of the first, second and third processors are executing the same interrupt at the same time.
Claim 32
Dependent Claim
84 words
A computer system comprising: a) multiple CPUs; b) redundant modules accessed by said CPUs via separate ports from each CPU, the modules voting requests received from the CPUs; c) redundant I/O processors accessed by said CPUs via said ports and said modules; d) a plurality of I/O devices each of which is accessed by one of said I/O processors as designated by data stored by said CPUs, said data being alterable by said CPUs to redesignate the I/O processor accessing each said I/O device.
Claim 33
Dependent Claim
22 words
A system according to claim 32 wherein said multiple CPUs execute the same instruction stream, and wherein said modules are memory modules.
Claim 34
Dependent Claim
50 words
A system according to claim 32 including means for detecting faults in said I/O processors, wherein said data stored by said CPUs is the addresses of registers in said I/O devices, and wherein said each one of said I/O processors is accessed by said CPUs via two of said modules.
Claim 35
Independent Claim
101 words
A method of operating a computer system having multiple CPUs comprising the steps of: a) accessing redundant modules by said multiple CPUs via separate ports from each CPU, including voting requests received from the CPUs by the modules; b) accessing redundant I/O processors by said CPUs via said ports and said modules; c) accessing a plurality of I/O devices via said I/O processors, each of the I/O devices being accessed by one of said I/O processors as designated by data stored by said CPUs, said data being alterable by said CPUs to redesignate the I/O processor accessing each said I/O device.
Claim 36
Dependent Claim
22 words
A method according to claim 35 wherein said multiple CPUs execute the same instruction stream, and wherein said modules are memory modules.
Claim 37
Dependent Claim
33 words
A method according to claim 35 including the step of detecting faults in said I/O processors, and wherein said data stored by said CPUs is the addresses of registers in said I/O devices.
Claim 38
Dependent Claim
24 words
A method according to claim 35 wherein said each one of said I/O processors is accessed by said CPUs via two of said modules.
References Cited (Backward Citations)
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