Patent EP0440192A1 successfully refreshed from Google Patents.
EP0440192A1
Expired / Lapsed
EP
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ECL circuit constituted in semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1991-01-30
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Granted: —
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Expires: 2011-01-30
Abstract
Abstract An ECL circuit is designed such that at the beginning of the falling of the output level, the current flowing to an output terminal (11) is rapidly led in the direction where it will be reduced, the potential of the output terminal (11) at this time is directly detected, and a pull down transistor (15) is controlled through a feedback loop, thus assuring high-speed operation and low power consumption. A control circuit is provided to regulate the collector current of the pull down transistor (15), which is used to drop the level of the potential at the output terminal (11). This control circuit is so designed that the base current of the pull down transistor (15) is controlled by the operation of another, single transistor (12), and no capacitor which will obstruct the circuit integration is employed to drive the pull down transistor (15). The structure of this circuit is therefore advantageous in realizing higher integration.
Inventors
- 👤 Takeshi C/O Intellectual Property Div. Sugoh
- 👤 Yasuhiro C/O Intellectual Property Div. Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 03:17
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
119 words
An ECL circuit constituted in a semiconductor integrated circuit, comprising: first and second transistors (1, 2) having emitters connected to each other to form a differential pair; an input terminal (5) connected to a base of said first transistor (1); a third transistor (10) having a base connected to a collector of said first transistor (1), and an emitter connected to an output terminal (11); a fourth transistor (15) having a base connected through a diode (14) to a collector of said second transistor (2), and a collector connected to said output terminal (11); and a control circuit for controlling a collector current of said second transistor (2) in accordance with a collector current of said fourth transistor (15).
Claim 2
Dependent Claim
35 words
An ECL circuit according to claim 1, characterized in that said control circuit directly detects a potential at said output terminal (11) and performs feedback control of a base current of said fourth transistor (150).
Claim 3
Dependent Claim
62 words
An ECL circuit according to claim 1, characterized in that said control circuit comprises a fifth transistor (12) having a collector and an emitter connected between a predetermined potential point, determined by dividing a load resistor element provided at said collector of said second transistor (2), and said output terminal (11), said fifth transistor (12) being biased by a predetermined base potential.
Claim 4
Dependent Claim
110 words
An ECL circuit constituted in a semiconductor integrated circuit, comprising: a differential pair including first and second transistors (1, 2) having emitters connected to each other; a third transistor (10) having a base connected to one collector output of said differential pair; a fourth transistor (15) having a base connected to the other collector output of said differential pair a logic output terminal (11) connected to an emitter of said third transistor (10) and a collector of said fourth transistor (15); and a fifth transistor (12) for detecting a potential at said logic output terminal (11) and performing a feedback control of a collector output of said second transistor (2).
Claim 5
Dependent Claim
56 words
An ECL circuit according to claim 4, characterized in that said fifth transistor (12) has a collector and an emitter connected between a predetermined potential point, determined by dividing a load resistor element provided at said collector of said second transistor (2), and said logic output terminal (11), and is biased by a predetermined base potential.
Claim 6
Dependent Claim
274 words
An ECL logic circuit constituting an inverter circuit, comprising: first and second transistors (1, 2) forming a differential pair and each having a collector coupled to a first potential (V SS ) and an emitter coupled to a second potential (V EE ); a constant-current supply (3) inserted between said emitters of said first and second transistors (1, 2) and said second potential (V EE ); an input terminal (5) connected to a base of said first transistor (1); a first resistor element (6) inserted between said collector of said first transistor (1) and said first potential (V SS ); a reference potential (V ref ) connected to a base of said second transistor (2); second and third resistor elements (8, 9) inserted between said collector of said second transistor (2) and said first potential (V SS ); a third transistor (10) having a base connected to said collector of said first transistor (1), a collector connected to said first potential (V SS ) and an emitter connected to an output terminal (11); a fourth transistor (15) having a collector connected to said output terminal (11) and an emitter connected to a first predetermined potential (V TT ); a fourth resistor element (16) connected between a base and said emitter of said fourth transistor (15); a diode (14) inserted between said collector of said second transistor (2) and said base of said fourth transistor (15); and a fifth transistor (12) having an emitter connected to said output terminal (11), a collector connected to a series-connected point of said second and third resistor elements (8, 9) and a base connected to a second predetermined potential.
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