Metal insulator semiconductor type dynamic random access memory device

Claim 2

A dynamic random access memory device including a substrate (11), and a plurality of paris of sources (21, 32) and drains (25) of transistors formed in said substrate and located within an area defined by field oxidation films (29) formed on said substrate, said transistors being arrayed in the form of a matrix, characterized in that said device comprises gate electrodes (24) formed on gate oxidation films (32) formed on said substrate and located between said pairs of sources and drains, said gate electrodes extending in a first direction (Y) perpendicular to the direction of a channel formed between said paired source and drain; a plurality of word lines (22) formed on said field oxidation films and extending in a second direction (X) identical to the direction of said channel, said word lines being integrally formed with said gate electrodes; a plurality of bit lines (21) formed in said substrate and including said sources as portions thereof, said bit lines extending in the first direction perpendicular to the direction of said channel; an insulating film (30) covering said word lines and said gate electrodes and including contact holes (23); and a plurality of storage capacitors (26, 27, 28) each making connect with related one of said drains through related one of said contact holes formed in said insulating film, each of said storage capacitors including a storage electrode (26) extending above related one of said gate electrodes, related one of said word lines and said field oxidation films, a dielectric film (28) surrounding said storage electrode, and an opposed electrode (27) so as to cover said dielectric film.

Claim 3

A dynamic random access memory device as claimed in claim 1, characterized in that each of said word lines (22) extends in the second direction between neighboring transistors arranged in the first direction.

Claim 4

A dynamic random access memory device as claimed in any of claims 1 and 2, characterized in that said gate electrodes (24) extend from the related word lines (22) in the same direction.

Claim 5

A dynamic random access memory device as claimed in any of claims 1 to 3, characterized in that said bit lines (21) include a first bit line coupled to the sources of said transistors arranged on both sides of said first bit line.

Claim 6

A dynamic random access memory device as claimed in any of claims 1 to 3, characterized in that said bit lines (21) include a second bit line coupled to the source of said transistors located on either side of said second bit line.

Claim 7

A dynamic random access memory device as claimed in any of claims 1 to 5, characterized by further comprising a plurality of sense amplifiers (S/A) each amplifying the potential difference between two related bit lines among said plurality of bit lines, said sense amplifiers being arranged in said second direction (X) identical to the direction of said channel.

Claim 8

A dynamic random access memory device as claimed in any of claims 1 to 6, characterized in that the distance between neighboring bit lines (21) is larger than the distance between neighboring word lines (22).

Claim 9

A dynamic random access memory device including a substrate (50), and a plurality of paris of sources (51) and drains (55) of transistors formed in said substrate and located within an area defined by field oxidation films (59) formed on said substrate, said transistors being arrayed in the form of a matrix, characterized in that said device comprises a plurality of word lines (52) formed on said field oxidation films and gate oxidation films (62) formed on said substrate, said word lines extending in a first direction identical to the direction of a channel formed between said paired source and drain and extending above said sources and drains covered by said gate oxidation films, said word lines having contact holes (53) through which said drains are exposed, said word lines being served as gate electrodes of said transistors; an insulating film (60) covering said word lines and a sidewall of each of said contact holes (53) and partially covering said drains (55) exposed through said contact holes; a plurality of bit lines (51) formed in said substrate and including said sources as portions thereof, said bit lines extending in a second direction (Y) perpendicular to the direction of said channel and said first direction; and a plurality of storage capacitors (56, 57, 58) each making connect with related one of said drains (55) through related one of said contact holes formed in said insulating film, each of said storage capacitors including a storage electrode (56) extending above said word lines, and said field oxidation films, a dielectric film (58) surrounding said storage electrode, and an opposed electrode (57) so as to cover said dielectric film.

Claim 10

A dynamic random access memory device including a substrate (50), and a plurality of paris of sources (51) and drains (55) of transistors formed in said substrate and located within an area defined by field oxidation films (59) formed on said substrate, said transistors being arrayed in the form of a matrix, characterized in that said device comprises a plurality of word lines (52) formed on said field oxidation films and gate oxidation films (62) formed on said substrate, said word lines extending in a first direction identical to the direction of a channel formed between said paired source and drain and extending above said sources and drains covered by said gate oxidation films, said word lines having contact holes (53) through which said drains are exposed, said word lines being served as gate electrodes of said transistors; an insulating film (60) covering said word lines and a sidewall of each of said contact holes (53) and partially covering said drains (55) exposed through said contact holes; a plurality of bit lines (51) formed in said substrate and including said sources as portions thereof, said bit lines extending in a second direction (Y) perpendicular to the direction of said channel and said first direction; and a plurality of storage capacitors (56, 57, 58) each making connect with related one of said drains (55) through related one of said contact holes formed in said insulating film, each of said storage capacitors including a storage electrode (56) extending above said word lines, and said field oxidation films, a dielectric film (58) surrounding said storage electrode, and an opposed electrode (57) so as to cover said dielectric film.

Claim 11

A dynamic random access memory device as claimed in claim 8, characterized in that said word lines (52) are wider than said contact holes (53).

Claim 12

A dynamic random access memory device as claimed in any of claims 8 and 9, characterized in that each of said storage capacitors has almost the same width as each of said word lines.

Claim 13

A dynamic random access memory device as claimed in any of claims 8 to 10, characterized in that said said insulating film (60) includes a portion (63) formed by a reactive ion etching process, and said portion covers said sidewall of each of said contact holes (53).

Claim 14

A dynamic random access memory device as claimed in any of claims 8 to 111, characterized in that said storage electrode is self-aligned with respect to related one of said word lines (52) and is in contact with said related one of said drains (53).

Claim 15

A dynamic random access memory device as claimed in any of claims 8 to 12, characterized by further comprising a plurality of sense amplifiers (S/A) each amplifying the potential difference between two related bit lines among said plurality of bit lines (51), said sense amplifiers being arranged in said first direction identical to the direction of said channel.

Claim 16

A dynamic random access memory device as claimed in any of claims 8 to 13, characterized in that the distance between neighboring bit lines (51) is larger than the distance between neighboring word lines (52).

Claim 17

A dynamic random access memory device as claimed in any of claims 8 to 14, characterized in that said bit lines (51) includes a first bit line coupled to the sources of said related transistors arranged on both sides of said first bit line.

Claim 18

A dynamic random access memory device including a substrate (80), and a plurality of paris of sources (84) and drains (85) of transistors formed in said substrate and located within an area defined by field oxidation films (89) formed on said substrate, said transistors being arrayed in the form of a matrix, characterized in that said device comprises gate electrodes (92) formed on gate oxidation films (93) formed on said substrate and located between said pairs of sources and drains, said gate electrodes extending in a first direction (Y) perpendicular to the direction of a channel formed between said paired source and drain; a plurality of word lines (82) formed on said field oxidation films and extending in a second direction (X) identical to the direction of said channel, said word lines being integrally formed with said gate electrodes; an insulating film (90, 91) covering said word lines and gate electrodes and including first and second contact holes (83′, 83); a plurality of bit lines (81) formed on said insulating film and making contact with said sources (84) through said first contact holes (83′) formed in said insulating film, said bit lines extending in the first direction (Y) perpendicular to the direction of said channel; and a plurality of storage capacitors (86, 87, 88) each making connect with related one of said drains (85) through said second contact hole (83) formed in said insulating film, each of said storage capacitors including a storage electrode (86) extending above related one of said gate electrodes, related one of said word lines and said field oxidation films, a dielectric film (88) surrounding said storage electrode, and an opposed electrode (87) so as to cover said dielectric film.

Claim 19

A dynamic random access memory device including a substrate (80), and a plurality of paris of sources (84) and drains (85) of transistors formed in said substrate and located within an area defined by field oxidation films (89) formed on said substrate, said transistors being arrayed in the form of a matrix, characterized in that said device comprises gate electrodes (92) formed on gate oxidation films (93) formed on said substrate and located between said pairs of sources and drains, said gate electrodes extending in a first direction (Y) perpendicular to the direction of a channel formed between said paired source and drain; a plurality of word lines (82) formed on said field oxidation films and extending in a second direction (X) identical to the direction of said channel, said word lines being integrally formed with said gate electrodes; an insulating film (90, 91) covering said word lines and gate electrodes and including first and second contact holes (83′, 83); a plurality of bit lines (81) formed on said insulating film and making contact with said sources (84) through said first contact holes (83′) formed in said insulating film, said bit lines extending in the first direction (Y) perpendicular to the direction of said channel; and a plurality of storage capacitors (86, 87, 88) each making connect with related one of said drains (85) through said second contact hole (83) formed in said insulating film, each of said storage capacitors including a storage electrode (86) extending above related one of said gate electrodes, related one of said word lines and said field oxidation films, a dielectric film (88) surrounding said storage electrode, and an opposed electrode (87) so as to cover said dielectric film.

Claim 20

A dynamic random access memory device as claimed in claim 16, characterized in that each of said word lines (82) extends in the second direction (X) between neighboring transistors arranged in the first direction (Y).

Claim 21

A dynamic random access memory device as claimed in any of claims 16 and 17, characterized in that said bit lines (81) include a first bit line coupled to the sources (84) of said transistors arranged on both sides of said first bit line.

Claim 22

A dynamic random access memory device as claimed in any of claims 16 to 18, characterized by further comprising a plurality of sense amplifiers (S/A) each amplifying the potential difference between two related bit lines among said plurality of bit lines (81), said sense amplifiers being arranged in said second direction (X) identical to the direction of said channel.

Claim 23

A dynamic random access memory device as claimed in any of claims 16 to 19, characterized in that the distance between neighboring bit lines (81) is larger than the distance between neighboring word lines (80).

Claim 24

A dynamic random access memory device including a substrate (121), and a plurality of paris of sources (114) and drains (115) of transistors formed in said substrate and located within an area defined by field oxidation films (119) formed on said substrate, said transistors being arrayed in the form of a matrix, characterized in that a plurality of word lines (112) formed said field oxidation films and gate oxidation films formed on said substrate, said word lines extending in a first direction (X) identical to the direction of a channel formed between said paired source and drain and extendihg above said sources and drains covered by said gate oxidation films, said word lines having first and second contact holes (130, 129), said drains being exposed through said related first contact holes (130), said word lines being served as gate electrodes of said transistors; an insulating film (128) covering said word lines and a sidewall of each of said first and second contact holes and partially covering said drains and sources exposed through said first and second contact holes; a plurality of bit lines (111) formed on said insulating film and making contact with related sources (114) through said second contact holes (129) formed in said insulating films, said bit lines extending in a second direction perpendicular to the direction of said channel and said first direction; and a plurality of storage capacitors (116, 117, 118, 132) each making connect with related one of said drains through related one of said first contact holes (130) formed in said insulating film, each of said storage capacitors including a storage electrode (116, 133) extending above related one of said word lines and said field oxidation films, a dielectric film (118) surrounding said storage electrode, and an opposed electrode (117) so as to cover said dielectric film.

Claim 25

A dynamic random access memory device including a substrate (121), and a plurality of paris of sources (114) and drains (115) of transistors formed in said substrate and located within an area defined by field oxidation films (119) formed on said substrate, said transistors being arrayed in the form of a matrix, characterized in that a plurality of word lines (112) formed said field oxidation films and gate oxidation films formed on said substrate, said word lines extending in a first direction (X) identical to the direction of a channel formed between said paired source and drain and extendihg above said sources and drains covered by said gate oxidation films, said word lines having first and second contact holes (130, 129), said drains being exposed through said related first contact holes (130), said word lines being served as gate electrodes of said transistors; an insulating film (128) covering said word lines and a sidewall of each of said first and second contact holes and partially covering said drains and sources exposed through said first and second contact holes; a plurality of bit lines (111) formed on said insulating film and making contact with related sources (114) through said second contact holes (129) formed in said insulating films, said bit lines extending in a second direction perpendicular to the direction of said channel and said first direction; and a plurality of storage capacitors (116, 117, 118, 132) each making connect with related one of said drains through related one of said first contact holes (130) formed in said insulating film, each of said storage capacitors including a storage electrode (116, 133) extending above related one of said word lines and said field oxidation films, a dielectric film (118) surrounding said storage electrode, and an opposed electrode (117) so as to cover said dielectric film.

Claim 26

A dynamic random access memory device as claimed in claim 21, characterized in that said word lines (112) are wider than said contact holes.

Claim 27

A dynamic random access memory device as claimed in any of claims 21 and 22, characterized in that each of said storage capacitors has almost the same width as each of said word lines.

Claim 28

A dynamic random access memory device as claimed in any of claims 21 to 23, characterized in that said said insulating film includes a portion (131) formed by a reactive ion etching process, and said portion covers said sidewall of each of said first and second contact holes (130, 129).

Claim 29

A dynamic random access memory device as claimed in any of claims 21 to 24, characterized in that said storage electrode (116, 133) includes a portion (133) which is self-aligned with respect to related one of said word lines (112) and is in contact with said related one of said drains (115).

Claim 30

A dynamic random access memory device as claimed in any of claims 21 to 25, characterized by further comprising a plurality of sense amplifiers (S/A) each amplifying the potential difference between two related bit lines among said plurality of bit lines, said sense amplifiers being arranged in said first direction (X) identical to the direction of said channel.

Claim 31

A dynamic random access memory device as claimed in any of claims 21 to 26, characterized in that the distance between neighboring bit lines (111) is larger than the distance between neighboring word lines (112).

Claim 32

A dynamic random access memory device as claimed in any of claims 21 to 27, characterized in that said bit lines (111) includes a first bit line coupled to the sources of said transistors arranged on both sides of said first bit line.

Claim 33

A dynamic random access memory device as claimed in any of claims 21 to 28, characterized in that said storage electrode includes a leader portion (133) which is in contact with related one of said drains, and an electrode portion (116) laid on and in contact with said leader portion.