Microcomputer system for digital signal processing

Claim 2

A microprocessor system comprising: a microprocessor device formed in a single integrated circuit and having data input/output terminals and address output terminals; memory means external to the microcomputer device having an address input and data output means; input/output peripheral means for transfer of information to or from external equipment; external address bus means coupled to the address output terminals of the microprocessor device and to the peripheral means and the address input of the memory means; external data bus means coupled to the data input/output terminals of the microprocessor device and to the peripheral means and the data output means of the memory means; the microprocessor device comprising: an arithmetic/logic unit having data input and data output; a data memory having an address input and having data input/output means; internal data bus means coupled to the data input and data output of the arithmetic/logic unit and coupled to the data input/output means.'of the data memory; internal program memory means having an address input and having a memory output, the program memory means storing instruction words; program address means connected to the address input of the program memory means; control means for generating controls in response to instruction words, the controls defining operation of the arithmetic/logic unit and transfer to and from the internal bus means; internal program bus means coupled to said memory output to receive instruction words, to said control means to deliver instruction words to said control means, and to said program address means to transfer program addresses; timing means for establishing an operating cycle during which data may be transferred from the data memory to the data input of the arithmetic/logic unit, the program address means applies an address to the address input of the program memory, and the control means receives an instruction word from said memory output.

Claim 3

A system according to claim 1 wherein successive operating cycles are overlapping.

Claim 4

A microprocessor system comprising: a microprocessor device formed in a single integrated circuit and having data input/output terminals and address output terminals; memory means external to the microprocessor device having an address input and data input/output means; input/output peripheral means for transfer of information to or from external equipment;- external address bus means coupled to the address output terminals of the microprocessor device and to the address input of the memory means; external data bus means coupled to the data input/output terminals of the microprocessor device and to the data input/output means of the memory means; the microprocessor device comprising: an arithmetic/logic unit having data input and data output; an accumulator receiving said data output of the arithmetic/logic unit and having an accumulator data output; a data memory having an address input and having data input/output means; internal data bus means coupled to the data input of the arithmetic/logic unit and said accumulator data output and coupled to the data input/output means of the data memory; an internal program memory having an address input and having a memory output, the program memory storing instruction words; program address means connected to the address input of the program memory means; control means for generating controls in response to instruction words, the controls defining operation of the arithmetic/logic unit and transfer to and from the internal bus means; internal program bus means coupled to said memory output, to said control means, and to said program address means; and timing means for establishing overlapping operating cycles during a single one of which data may be transferred from the data memory to the data input of the arithmetic/logic and the arithmetic/logic unit produces results to the accumulator for one instruction, the control means receives an instruction word from the memory output of the program memory for the next instruction, and the program address means applies an address to the address input of the program memory for another succeeding instruction.

Claim 5

A microprocessor system comprising: a microprocessor device formed in a single integrated circuit and having data input/output terminals and address output terminals; memory means external to the microprocessor device having an address input and data input/output means; input/output peripheral means for transfer of information to or from external equipment;- external address bus means coupled to the address output terminals of the microprocessor device and to the address input of the memory means; external data bus means coupled to the data input/output terminals of the microprocessor device and to the data input/output means of the memory means; the microprocessor device comprising: an arithmetic/logic unit having data input and data output; an accumulator receiving said data output of the arithmetic/logic unit and having an accumulator data output; a data memory having an address input and having data input/output means; internal data bus means coupled to the data input of the arithmetic/logic unit and said accumulator data output and coupled to the data input/output means of the data memory; an internal program memory having an address input and having a memory output, the program memory storing instruction words; program address means connected to the address input of the program memory means; control means for generating controls in response to instruction words, the controls defining operation of the arithmetic/logic unit and transfer to and from the internal bus means; internal program bus means coupled to said memory output, to said control means, and to said program address means; and timing means for establishing overlapping operating cycles during a single one of which data may be transferred from the data memory to the data input of the arithmetic/logic and the arithmetic/logic unit produces results to the accumulator for one instruction, the control means receives an instruction word from the memory output of the program memory for the next instruction, and the program address means applies an address to the address input of the program memory for another succeeding instruction.

Claim 6

A system according to claim 1, 2 or 3 wherein the internal data bus means comprises a bus N bits in width and the data output of the arithmetic/logic unit is 2N bits.

Claim 7

A system according to claim 3 wherein said accumulator data output is coupled to one said data input of the arithmetic/logic unit, and is also separately connected to the data bus means via high and low N bit word transfer means.

Claim 9

A microcomputer device formed in a single semiconductor unit comprising: an arithmetic/logic unit having data input and data output; an accumulator having an input connected to said data output and an accumulator output; a data memory having an address input and having data input/output means; data bus means coupled to the data input of the arithmetic/logic unit and to said accumulator output and coupled to the data input/output means of the data memory; means connecting the accumulator output to a data input of the arithmetic/logic unit separate from the data bus means; data input/output terminals for coupling to circuits external to the semiconductor unit connected to the data bus means; a shifter in the coupling from the data bus means to a data input of the arithmetic/logic unit for shifting a selectable number of bits under control of the instruction word; a program memory having an address input and having a memory output, the program memory storing instruction words; program address means connected to the address input of the program memory means; control means for generating controls in response to instruction words, the controls defining operation of the arithmetic/logic unit and transfer to and from the bus means; program bus means coupled to said instruction output, to said control means, and to said program address means; and timing means for establishing overlapping operating cycles during a single one of which data may be transferred from the data memory to a data input of the arithmetic/logic unit via said shifter, and the arithmetic/logic unit produces results to the accumulator for one instruction, the control means receives an instruction word from said memory output via said program bus means for the next instruction, and the program address means applies an address to the address input of the program memory for another following instruction.

Claim 10

A microcomputer device formed in a single semiconductor unit comprising: an arithmetic/logic unit having data input and data output; an accumulator having an input connected to said data output and an accumulator output; a data memory having an address input and having data input/output means; data bus means coupled to the data input of the arithmetic/logic unit and to said accumulator output and coupled to the data input/output means of the data memory; means connecting the accumulator output to a data input of the arithmetic/logic unit separate from the data bus means; data input/output terminals for coupling to circuits external to the semiconductor unit connected to the data bus means; a shifter in the coupling from the data bus means to a data input of the arithmetic/logic unit for shifting a selectable number of bits under control of the instruction word; a program memory having an address input and having a memory output, the program memory storing instruction words; program address means connected to the address input of the program memory means; control means for generating controls in response to instruction words, the controls defining operation of the arithmetic/logic unit and transfer to and from the bus means; program bus means coupled to said instruction output, to said control means, and to said program address means; and timing means for establishing overlapping operating cycles during a single one of which data may be transferred from the data memory to a data input of the arithmetic/logic unit via said shifter, and the arithmetic/logic unit produces results to the accumulator for one instruction, the control means receives an instruction word from said memory output via said program bus means for the next instruction, and the program address means applies an address to the address input of the program memory for another following instruction.

Claim 11

A device according to claim 7 wherein a multiplier having first and second operand inputs and a result output is included in said semiconductor unit, the first and second operand inputs being loaded from said data bus means, one of said first and second operand inputs including temporary storage means, said result output beinga product register, and selector means controlled by said control means connecting either said product register or the output of said shifter to said data input of the arithmetic/logic unit.

Claim 12

A multiplier circuit comprising: a) first input means for a first operand of N bits; b) second input means for a second operand of M bits; c) N/2 decoder means each receiving two of said N bits from said frist input means and producing a plurality of controls; d) N/2 static adder levels, each level including a control section receiving said controls from one of said decoder means, each level except the lowest containing at least M parallel binary adder stages, each stage of each level receiving one of said M bits from the second input means, partial products and carry being connected from one level to the next higher level, but no carry being coupled along adder stages within a level, e) at least M+N adder stages with ripple carry, each stage receiving partial product outputs from said static adder levels, the MSB adder stages receiving partial product bits from the highest level of said static adder levels, the two LSB adder stages receiving two partial product bits from the lowest level of said static adder level, and each pair of adder stages between LSBs and MSBs receiving two partial product bits from LSB stages of corresponding intervening static adder levels.

Claim 13

A multiplier circuit comprising: a) first input means for a first operand of N bits; b) second input means for a second operand of M bits; c) N/2 decoder means each receiving two of said N bits from said frist input means and producing a plurality of controls; d) N/2 static adder levels, each level including a control section receiving said controls from one of said decoder means, each level except the lowest containing at least M parallel binary adder stages, each stage of each level receiving one of said M bits from the second input means, partial products and carry being connected from one level to the next higher level, but no carry being coupled along adder stages within a level, e) at least M+N adder stages with ripple carry, each stage receiving partial product outputs from said static adder levels, the MSB adder stages receiving partial product bits from the highest level of said static adder levels, the two LSB adder stages receiving two partial product bits from the lowest level of said static adder level, and each pair of adder stages between LSBs and MSBs receiving two partial product bits from LSB stages of corresponding intervening static adder levels.

Claim 14

A multiplier circuit according to claim 9 wherein said decoders are identical Booth's decoders producing controls including add, subtract, shift and do-nothing.