US4125901A
Expired / Lapsed
US
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Electronic calculator or microprocessor having a multi-input arithmetic unit
Assignee: Texas Instruments Inc
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Filing: 1976-10-27
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Granted: 1978-11-14
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Expires: 1996-10-27
Abstract
Abstract An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having a arithmetic unit and memory system. The arithmetic unit and memory system include a plurality of operational registers and an arithmetic unit having two inputs and an output. A plurality of operational registers selector gates interconnect the operational registers and arithmetic unit for connecting any selected two of the plurality of operational registers to the inputs of the arithmetic unit. The plurality of operation register selector gates preferably comprise individual MOS transfer gates.
Inventors
- 👤 Thomas E. Merrow
- 👤 Stephen P. Hamilton
- 👤 Larry L. Miles
- 👤 Charles P. Grant, Jr., deceased
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:44
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; G06F9/3012; G06F9/30134
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
114 words
An arithmetic unit and memory system for an electronic microprocessor comprising: (a) a plurality of operational registers, each of said operational registers having an input and first and second outputs, (b) an arithmetic unit having two inputs and an output and having means for performing arithmetic operations on data received at the inputs thereof and for communicating the results of said arithmetic operations to the output thereof, and (c) a plurality of operational register selector gates interconnecting said plurality of operational registers and said arithmetic unit for connecting a selected one of said first and second outputs of a selected one of said operational registers to one of the inputs of said arithmetic unit.
Claim 2
Dependent Claim
114 words
An arithmetic unit and memory system for an electronic microprocessor comprising: (a) a plurality of operational registers, each of said operational registers having an input and first and second outputs, (b) an arithmetic unit having two inputs and an output and having means for performing arithmetic operations on data received at the inputs thereof and for communicating the results of said arithmetic operations to the output thereof, and (c) a plurality of operational register selector gates interconnecting said plurality of operational registers and said arithmetic unit for connecting a selected one of said first and second outputs of a selected one of said operational registers to one of the inputs of said arithmetic unit.
Claim 3
Dependent Claim
27 words
The system according to claim 1, further including means for connecting the output of said arithmetic unit to a selected one of said plurality of operational registers.
Claim 4
Dependent Claim
58 words
The system according to claim 2, wherein said plurality of operational register selector gates comprises: (a) first gating means for selectively coupling the outputs of said operational registers to a first input of said arithmetic unit, and (b) second gating means for selectively connecting the outputs of said operational registers to a second input of said arithmetic unit.
Claim 5
Dependent Claim
58 words
A system according to claim 3, wherein said first and second gating means include first means for selectively coupling the first and second outputs of said operational registers to a common point associated with each one of said operational registers and second means for interconnecting said common points with the first and second inputs of said arithmetic unit.
Claim 6
Dependent Claim
54 words
The system according to claim 4, wherein said second means includes a plurality of single transistors coupling the common point for each operational register to the first input of said arithmetic unit and another plurality of single transistors coupling the common point for each operational register to the second input of said arithmetic unit.
Claim 7
Dependent Claim
59 words
The system as defined in claim 5, wherein said first means includes a plurality of single transistors each coupling the first output of said plurality of registers to the common point associated with said registers and another plurality of single transistors each coupling the second output of said plurality of registers to the common point associated with said registers.
Claim 8
Dependent Claim
172 words
In an electronic microprocessor having a memory for storing a plurality of instruction words, means for outputting the instruction words stored in said memory, a plurality of operational registers for storing numeric data, each said operational register having an input and a first output, an arithmetic unit for performing arithmetic operations on the numeric data stored in said operational registers, decoder means for decoding the instruction words outputted from said memory, and a plurality of register selector gates, responsive to said decoder means, for communicating the numeric data stored in said operational registers to said arithmetic unit, the improvement comprising a second output associated with each of said operational registers for use during left hand shifting of data stored in said operational registers and wherein said operational register selector gates include first gating means for selectively coupling the first and second outputs of said operational registers to a common point associated with each one of said operational registers and second gating means for selectively coupling said common points with said arithmetic unit.
Claim 9
Dependent Claim
172 words
In an electronic microprocessor having a memory for storing a plurality of instruction words, means for outputting the instruction words stored in said memory, a plurality of operational registers for storing numeric data, each said operational register having an input and a first output, an arithmetic unit for performing arithmetic operations on the numeric data stored in said operational registers, decoder means for decoding the instruction words outputted from said memory, and a plurality of register selector gates, responsive to said decoder means, for communicating the numeric data stored in said operational registers to said arithmetic unit, the improvement comprising a second output associated with each of said operational registers for use during left hand shifting of data stored in said operational registers and wherein said operational register selector gates include first gating means for selectively coupling the first and second outputs of said operational registers to a common point associated with each one of said operational registers and second gating means for selectively coupling said common points with said arithmetic unit.
Claim 10
Dependent Claim
64 words
The microprocessor according to claim 7, wherein said arithmetic unit has first and second inputs, wherein said second gating means comprises a first plurality of transistors coupling the common point for each operational register to the first input of said arithmetic unit and a second plurality of transistors coupling the common point for each operational register to the second input of said arithmetic unit.
Claim 11
Dependent Claim
71 words
An arithmetic unit and memory system for an electronic microprocessor comprising: (a) a plurality of operational registers, each of said operational registers having an input and two outputs; (b) an arithmetic unit; (c) first gating means for selectively coupling the two outputs of said operational registers to common points associated with each one of said operational registers; and (d) second gating means selectively coupling said common points and said arithmetic unit.
Claim 12
Dependent Claim
71 words
An arithmetic unit and memory system for an electronic microprocessor comprising: (a) a plurality of operational registers, each of said operational registers having an input and two outputs; (b) an arithmetic unit; (c) first gating means for selectively coupling the two outputs of said operational registers to common points associated with each one of said operational registers; and (d) second gating means selectively coupling said common points and said arithmetic unit.
Claim 13
Dependent Claim
73 words
The arithmetic unit and memory system according to claim 9, wherein said first gating means comprises a first plurality of single transistors each coupling a first one of the two outputs of said operational registers to the common point associated with said operational registers and a second plurality of single transistors each coupling a second one of the two outputs of said operational registers to the common point associated with said operational registers.
Claim 14
Dependent Claim
70 words
The arithmetic unit and memory system according to claim 9, wherein each of said operational registers comprises a multi-stage shift register including an input stage and an output stage and wherein one of the two outputs from each operational register is provided by the output stage of the shift register and the other of the two outputs from each operational register is provided by another stage of the shift register.
Claim 15
Dependent Claim
67 words
The arithmetic unit and memory system according to claim 9, wherein said arithmetic unit has first and second inputs and wherein said second gating means includes first means for selectively coupling the common points of said operational registers to said first input of said arithmetic unit and second means for selectively coupling the common points of said operational registers to said second input of said arithmetic unit.
Claim 16
Dependent Claim
67 words
The arithmetic unit and memory system according to claim 12, wherein said first means comprises a first plurality of single transistors, each of which couples one of said common points to the first input of said arithmetic unit and wherein said second means comprises a second plurality of single transistors each of which couples one of said common points to the second input of said arithmetic unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-13 | 1982-05-15 | 1982-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-13 | 1986-05-15 | 1986-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-13 | 1990-05-15 | 1990-11-14 | $7700.00 | Window Closed / Lapsed |