Digital serial arithmetic unit

Claim 2

A data processing device which comprises a shift register having a plurality of series-connected stages, each of which is composed of a plurality of bit cells, at least one of the cells for storing a first information and the remaining cells for storing a second information; circulation path means connected between the input and the output of said shift register; means for shifting the content stored in said shift register from one bit to another and from one stage to another; said circulation path means including gate means for passing said first information therethrough during a timing corresponding to said first information and for passing said second information therethrough during a timing corresponding to said second information; and said circulation path means further including full adder having an input for receiving the second information from said shift register via said gate means, said full adder for performing an arithmetic operation of calculation between said second information received thereby and information applied to another input of said full adder; said full adder comprising a first half adder having a pair of input terminals for respectively receiving two binary coded informations to be added to each other, a first AND gate having a pair of input terminals for respectively receiving said binary coded informations, a second AND gate having one input terminal for receiving one of said binary coded informations and another input terminal for receiving a carry signal, a third AND gate having one input terminal for receiving the other of said binary coded informations and another input terminal for receiving said carry signal, a one-bit delay circuit responsive to an output signal from any one of said first, second and third AND gates for delaying said output signal for a period of time corresponding to one bit thereby to subsequently generate a one-bit delayed carry signal, a second half adder having a pair of input terminals for respectively receiving an output signal from said first half adder and said carry signal from said one-bit delay circuit, an inhibit gate element for inhibiting the application of the carry signal from the one-bit delay circuit to said second and third AND gates and said second half adder for a predetermined bit timing, and a gate element capable of feeding the one-bit delayed carry signal back to the input of said one-bit delay circuit for maintaining said carry signal for a period of time corresponding to said bit timing.

Claim 3

A data processing device as claimed in claim 1, wherein said first and second informations are indicative of decimal point position and numeric values, respectively.

Claim 4

A data processing device which comprises a shift register having a plurality of series-connected stages, each of which is composed of a plurality of bit cells, at least one of the cells for storing a first information and the remaining cells for storing a second information; circulation path means connected between the input and the output of said shift register; means for shifting the content stored in said shift register from one bit to another and from one stage to another; said circulation path means including first gate means for passing said first information therethrough during a timing corresponding to said first information and for passing said second information therethrough during a timing corresponding to said second information; said circulation path means further including a full adder having an input for receiving the second information from said shift register via said first gate means, said full adder for performing an arithmetic operation of calculation between said second information received thereby and information applied to another input of said full adder; said full adder including a second gate means connected between an output terminal of the m-th stage m places rightwards from the first or input stage of said shift register, wherein m is an integer, and the last or output stage of said shift register for permitting the passage of a signal from said m-th stage to said output stage of said shift register therethrough in response to a signal applied to an input terminal of said second gate means; and a third gate means connected between the n-th stage n places rightwards from the input stage of said shift register, wherein n is an integer, and the output stage of said shift register for permitTing the passage of a signal from said n-th stage to said output stage of said shift register therethrough in response to a different signal applied to an input terminal of said third gate means, whereby, when said second gate means is conditioned to permit said passage, the data processing device processes the data information corresponding to m digits and, when said third gate means is conditioned to permit said passage, the data processing device processes the data information of n digits.

Claim 5

A data processing device which comprises a shift register having a plurality of series-connected stages, each of which is composed of a plurality of bit cells, at least one of the cells for storing a first information and the remaining cells for storing a second information; circulation path means connected between the input and the output of said shift register; means for shifting the content stored in said shift register from one bit to another and from one stage to another; said circulation path means including first gate means for passing said first information therethrough during a timing corresponding to said first information and for passing said second information therethrough during a timing corresponding to said second information; said circulation path means further including a full adder having an input for receiving the second information from said shift register via said first gate means, said full adder for performing an arithmetic operation of calculation between said second information received thereby and information applied to another input of said full adder; said full adder including a second gate means connected between an output terminal of the m-th stage m places rightwards from the first or input stage of said shift register, wherein m is an integer, and the last or output stage of said shift register for permitting the passage of a signal from said m-th stage to said output stage of said shift register therethrough in response to a signal applied to an input terminal of said second gate means; and a third gate means connected between the n-th stage n places rightwards from the input stage of said shift register, wherein n is an integer, and the output stage of said shift register for permitTing the passage of a signal from said n-th stage to said output stage of said shift register therethrough in response to a different signal applied to an input terminal of said third gate means, whereby, when said second gate means is conditioned to permit said passage, the data processing device processes the data information corresponding to m digits and, when said third gate means is conditioned to permit said passage, the data processing device processes the data information of n digits.

Claim 6

A data processing device which comprises a shift register having a plurality of series-connected stages, each of which is composed of a plurality of bit cells, at least one of the cells for storing a first information and the remaining cells for storing a second information; means for shifting the content stored in said shift register from one bit to another and from one stage to another; another shift register connected with said shift register and having one stage composed of the same number of bit cells as that of any of the stages of said shift register; a first AND gate means having a pair of input terminals, one of which receives a signal from the stage next to the output stage of said shift register and the other of which receives a signal generated either during a timing corresponding to the first information or during a timing corresponding to the second information when the content stored in said shift register is to be shifted rightwards; a second AND gate means having a pair of input terminals, one of which receives an output signal from the output stage of said shift register and the other of which receives a signal generated either during the timing corresponding to the first information or during the timing corresponding to the second information when the content stored in said shift register is to be circulated from the input stage to the output stage thereof; a third AND gate means having a pair of input terminals, one of which receives an output signal from said another shift register and the other of which receives a signal generated either during the timing corresponding to the first information or during the timing corresponding to the second information when the content stored in said shift register is to be shifted leftwards; a full adder having an input for receiving an output signal from any one of said first to third gate means for performing an arithmetic operation of calculation between said output signal received thereby and information applied to another input of said full adder; and means for applying the output from said full adder to said input of said shift register; said full adder comprising a first adder having a pair of input terminals for respectively receiving two binary coded informations to be added to each other, a first AND gate having a pair of input terminals for respectively receiving said binary coded informations, a second AND gate having one input terminal for receiving one of said binary coded informations and another input terminal for receiving a carry signal, a third AND gate having one input terminal for receiving the other of said binary coded informations and another input terminal for receiving said carry signal, a bone-bit delay circuit responsive to an output signal from any one of said first, second and third AND gates for delaying said output signal for a period of time corresponding to one bit thereby to subsequently generate a one-bit delayed carry signal, a second half adder having a pair of input terminals for respectively receiving an output signal from said first half adder and said carry signal from said one-bit delay circuit, an inhibit gate element for inhibiting the application of the carry signal from the one-bit delay circuit to said second and third AND gates and said second half adder for a predetermined bit timing, and a gate element for feeding the one-bit delayed carry signal back to the input of said one-bit delay circuit for maintaining said carry signal for a period of time correspondIng to said bit timing.

Claim 7

A data processing device which comprises a shift register having a plurality of series-connected stages, each of which is composed of a plurality of bit cells, at least one of the cells for storing a first information and the remaining cells for storing a second information; means for shifting the content stored in said shift register from one bit to another and from one stage to another; another shift register connected with said shift register and having one stage composed of the same number of bit cells as that of any of the stages of said shift register; a first AND gate means having a pair of input terminals, one of which receives a signal from the stage next to the output stage of said shift register and the other of which receives a signal generated either during a timing corresponding to the first information or during a timing corresponding to the second information when the content stored in said shift register is to be shifted rightwards; a second AND gate means having a pair of input terminals, one of which receives an output signal from the output stage of said shift register and the other of which receives a signal generated either during the timing corresponding to the first information or during the timing corresponding to the second information when the content stored in said shift register is to be circulated from the input stage to the output stage thereof; a third AND gate means having a pair of input terminals, one of which receives an output signal from said another shift register and the other of which receives a signal generated either during the timing corresponding to the first information or during the timing corresponding to the second information when the content stored in said shift register is to be shifted leftwards; a full adder having an input for receiving an output signal from any one of said first to third gate means for performing an arithmetic operation of calculation between said output signal received thereby and information applied to another input of said full adder; and means for applying the output from said full adder to said input of said shift register; said full adder comprising a first adder having a pair of input terminals for respectively receiving two binary coded informations to be added to each other, a first AND gate having a pair of input terminals for respectively receiving said binary coded informations, a second AND gate having one input terminal for receiving one of said binary coded informations and another input terminal for receiving a carry signal, a third AND gate having one input terminal for receiving the other of said binary coded informations and another input terminal for receiving said carry signal, a bone-bit delay circuit responsive to an output signal from any one of said first, second and third AND gates for delaying said output signal for a period of time corresponding to one bit thereby to subsequently generate a one-bit delayed carry signal, a second half adder having a pair of input terminals for respectively receiving an output signal from said first half adder and said carry signal from said one-bit delay circuit, an inhibit gate element for inhibiting the application of the carry signal from the one-bit delay circuit to said second and third AND gates and said second half adder for a predetermined bit timing, and a gate element for feeding the one-bit delayed carry signal back to the input of said one-bit delay circuit for maintaining said carry signal for a period of time correspondIng to said bit timing.

Claim 8

A data processing device as claimed in claim 4, wherein said first and second informations are indicative of decimal point position and numeric values, respectively.

Claim 9

A data processing device which comprises a shift register having a plurality of series-connected stages, each of which is composed of a plurality of bit cells, at least one of the cells for storing a first information and the remaining cells for storing a second information; circulation path means connected between the input and the output of said shift register; means for shifting the content stored in said shift register from one bit to another and from one stage to another; said circulation path means including gate means for passing said first information therethrough during a timing corresponding to said first information and for passing said second information therethrough during a timing corresponding to said second information; said circulation path means further including a full adder having an input adapted for receiving the second information from said shift register via said gate means, said full adder for performing an arithmetic operation of calculation between said second information received thereby and information applied to another input of said full adder; a display section coupled to said shift register and including a plurality of figure indicator tubes each comprising a plurality of first electrodes shaped to illuminate an information corresponding to the content of the information to be displayed and at least one control electrode; generator means for generating digit timing signals, each of which has the duration corresponding to five bit timings, for successively driving said figure indicator tubes in accordance with the content of the information to be displayed; means for decoding the information stored in said shift register and for generating a drive signal for selectively driving said first electrodes of said figure indicator tubes in response to said digit timing signal thereby to permit said display section to display the decoded information; and means for limiting the duration of a signal supplied to said control electrode of each figure indicator tube at one of the beginning and end of said duration in a period of time corresponding to one bit period.

Claim 10

A data processing device which comprises a shift register having a plurality of series-connected stages, each of which is composed of a plurality of bit cells, at least one of the cells for storing a first information and the remaining cells for storing a second information; circulation path means connected between the input and the output of said shift register; means for shifting the content stored in said shift register from one bit to another and from one stage to another; said circulation path means including gate means for passing said first information therethrough during a timing corresponding to said first information and for passing said second information therethrough during a timing corresponding to said second information; said circulation path means further including a full adder having an input adapted for receiving the second information from said shift register via said gate means, said full adder for performing an arithmetic operation of calculation between said second information received thereby and information applied to another input of said full adder; a display section coupled to said shift register and including a plurality of figure indicator tubes each comprising a plurality of first electrodes shaped to illuminate an information corresponding to the content of the information to be displayed and at least one control electrode; generator means for generating digit timing signals, each of which has the duration corresponding to five bit timings, for successively driving said figure indicator tubes in accordance with the content of the information to be displayed; means for decoding the information stored in said shift register and for generating a drive signal for selectively driving said first electrodes of said figure indicator tubes in response to said digit timing signal thereby to permit said display section to display the decoded information; and means for limiting the duration of a signal supplied to said control electrode of each figure indicator tube at one of the beginning and end of said duration in a period of time corresponding to one bit period.

Claim 11

A data processing device as claimed in claim 6, wherein said full adder comprises a first half adder having a pair of input terminals for respectively receiving two binary coded informations to be added to each other, a first AND gate having a pair of input terminals for respectively receiving said binary coded informations, a second AND gate having one input terminal for receiving one of said binary coded informations and another input terminal for receiving a carry signal, a third AND gate having one input terminal for receiving the other of said binary coded informations and another input terminal for receiving said carry signal, a one-bit delay circuit responsive to an output signal from any one of said first second and third AND gates for delaying said output signal for a period of time corresponding to one bit thereby to subsequently generate a one-bit delayed carry signal, a second half adder having a pair of input terminals for respectively receiving an output signal from said first half adder and said carry signal from said one-bit delay circuit, an inhibit gate element for inhibiting the application of the carry signal from the one-bit delay circuit to said second and third AND gates and said second half adder for a predetermined bit timing, and a gate element capable of feeding the one-bit delayed carry signal back to the input of said one-bit delay circuit for maintaining said carry signal for a period of time corresponding to said bit timing.

Claim 12

A data processing device as claimed in claim 6, wherein said first and second informations are indicative of decimal point position and numeric values, respectively.

Claim 13

A data processing device which compriSes a shift register having a plurality of series-connected stages, each of which is composed of a plurality of bit cells, at least one of the cells for storing a first information and the remaining cells for storing a second information; circulation path means connected between the input and the output of said shift register; means for shifting the content stored in said shift register from one bit to another and from one stage to another; said circulation path means including gate means for passing said first information therethrough during a timing corresponding to said first information and for passing said second information therethrough during a timing corresponding to said second information; said circulation path means further including a full adder having an input for receiving the second information from said shift register via said gate means, said full adder for performing an arithmetic operation of calculation between said second information received thereby and information applied to another input of said full adder; a display section coupled to said shift register and including a plurality of figure indicator tubes each comprising a plurality of first electrodes shaped to illuminate an information corresponding to the content of the information to be displayed and at least one control electrode; generator means for generating digit timing signals, each of which has the duration corresponding to five bit timings, for successively driving said figure indicator tubes in accordance with the content of the information to be displayed; means for decoding the information stored in said shift register and for generating a drive signal for selectively driving said first electrodes of said figure indicator tubes in response to said digit timing signal thereby to permit said display section to display the decoded information; and means for limiting the duration of a signal supplied to any of the first electrodes of each figure indicator tube at one of the beginning and end of said duration in a period of time corresponding to one bit period.

Claim 14

A data processing device which compriSes a shift register having a plurality of series-connected stages, each of which is composed of a plurality of bit cells, at least one of the cells for storing a first information and the remaining cells for storing a second information; circulation path means connected between the input and the output of said shift register; means for shifting the content stored in said shift register from one bit to another and from one stage to another; said circulation path means including gate means for passing said first information therethrough during a timing corresponding to said first information and for passing said second information therethrough during a timing corresponding to said second information; said circulation path means further including a full adder having an input for receiving the second information from said shift register via said gate means, said full adder for performing an arithmetic operation of calculation between said second information received thereby and information applied to another input of said full adder; a display section coupled to said shift register and including a plurality of figure indicator tubes each comprising a plurality of first electrodes shaped to illuminate an information corresponding to the content of the information to be displayed and at least one control electrode; generator means for generating digit timing signals, each of which has the duration corresponding to five bit timings, for successively driving said figure indicator tubes in accordance with the content of the information to be displayed; means for decoding the information stored in said shift register and for generating a drive signal for selectively driving said first electrodes of said figure indicator tubes in response to said digit timing signal thereby to permit said display section to display the decoded information; and means for limiting the duration of a signal supplied to any of the first electrodes of each figure indicator tube at one of the beginning and end of said duration in a period of time corresponding to one bit period.

Claim 15

A full adder which comprises a first half adder having a pair of input terminals for respectively receiving two binary coded information to be added to each other; a first AND gate having a pair of input terminals for respectively receiving said binary coded information; a second AND gate having one input terminal for receiving one of said binary coded informations and another input terminal for receiving a carry signal; a third AND gate having one input terminal for receiving the other of said binary coded informations and another input terminal for receiving said carry signal; a one-bit delay circuit responsive to an output signal from any one of said first second and third gate means for delaying said output signal for a period of time corresponding to one bit thereby to subsequently generate a one-bit delayed carry signal; a second half adder having a pair of input terminals for respectively receiving an output signal from said first half adder and said carry signal from said one-bit delay circuit; an inhibit gate element for inhibiting the application of the carry signal from the one-bit delay circuit to said second and third AND gates and said second half adder for a predetermined bit timing; and a gate element for feeding the one-bit delayed carry signal back to the input of said one-bit delay circuit for maintaining said carry signal for a period of time corresponding to said bit timing.

Claim 16

A full adder which comprises a first half adder having a pair of input terminals for respectively receiving two binary coded information to be added to each other; a first AND gate having a pair of input terminals for respectively receiving said binary coded information; a second AND gate having one input terminal for receiving one of said binary coded informations and another input terminal for receiving a carry signal; a third AND gate having one input terminal for receiving the other of said binary coded informations and another input terminal for receiving said carry signal; a one-bit delay circuit responsive to an output signal from any one of said first second and third gate means for delaying said output signal for a period of time corresponding to one bit thereby to subsequently generate a one-bit delayed carry signal; a second half adder having a pair of input terminals for respectively receiving an output signal from said first half adder and said carry signal from said one-bit delay circuit; an inhibit gate element for inhibiting the application of the carry signal from the one-bit delay circuit to said second and third AND gates and said second half adder for a predetermined bit timing; and a gate element for feeding the one-bit delayed carry signal back to the input of said one-bit delay circuit for maintaining said carry signal for a period of time corresponding to said bit timing.