Digital bit rate synchronizer for digital echo cancellers and similar signal processing devices

Claim 2

In a digital signal processing device of the type including a signal processor for receiving and processing first and second digital signals at first and second inputs, respectively, said second digital signal having at least first and second consecutive samples representing first and second values, respectively, and means for coupling said first and second digital signals to said first and second inputs, the improvement characterized in that said means for coupling comprises: interpolation and synchronization means for providing input samples to said second input, said input samples being derived from said second signal, synchronized in time with said first digital signal and representing values between said first and second values.

Claim 3

A digital signal processing device as defined in claim 1, wherein said interpolation and synchronization means comprises: means for generating from said second digital signal an interpolated signal representing at least one intermediate value between said first and second values; and sampling means synchronized with said first digital signal for sampling said interpolated signal and providing an interpolated signal sample to said second input.

Claim 4

A digital signal processing device as defined in claim 2, wherein said means for generating said interpolated signal comprises: digital to analog conversion means for converting said second digital signal to a first analog signal having at least first and second levels corresponding to said first and second values, respectively; and interpolating means, such as a low pass filter, for receiving said first analog signal and generating therefrom a second analog signal having gradual transitions between said first and second levels; and wherein said sampling means comprises: means for sampling said second analog signal in synchronism with said first digital signal; and analog to digital conversion means for converting said second analog signal samples to digital form and for supplying said digital form samples to said second input of said signal processor.

Claim 5

A signal processing device as defined in claim 3, wherein said means for sampling said second analog signal comprises: clock recovery means for generating a recoverd clock signal synchronized with said first digital signal; and sample-and-hold means clocked by said recovered clock signal for sampling said second analog signal.

Claim 6

A signal processing device as defined in claim 1, wherein said interpolation and synchronization means comprises: means for generating from said second digital signal a third digital signal representing at least one intermediate value between said first and second values; and sampling means synchronized with said first digital signal for sampling said third digital signal and providing third digital signal samples to said second input of said signal processor.

Claim 7

A signal processing device as defined in claim 5, wherein said means for generating said third digital signal comprises: means for determining a difference A between said first and second values; means for generating an incremental valve signal representing an incremental value A/m, where m is an integer; and means for repetitively adding said incremental value signal to said first value to generate said third digital signal changing from said first to said second values in increments of A/m.

Claim 8

A signal processing device as defined in claim 6, wherein said means for determining comprises: a first register for storing said first consecutive sample of said second digital signal; a second register for storing said second consecutive sample of said second digital signal; and comparison means for comparing the contents of said first and second registers.

Claim 9

A signal processing device as defined in claim 6, wherein said means for repetitively adding comprises: an accumulator receiving said incremental value signal as an accumulator input and providing an accumulator output, said accumulator adding said accumulator input and output in response to an accumulator clock signal; clock means for generating clock pulses at a rate of m fsi , where f si is the sample rate of said second digital signal; and comparison means for comparing said accumulator output to said second value, said comparison means enabling said clock means when said accumulator output and second value are different and disabling said clock means when the value of said accumulator output reaches said second value.

Claim 10

A digital signal processing device as defined in claim 8, wherein said clock means comprises: clock recovery means receiving said second digital signal and generating a clock signal having a rate f si ; clock multiplication means for receiving the output of said clock recovery means and providing a clock signal having a rate m fsi ; and gate means for passing the output of said clock multiplication means to said accumulator when enabled, said gate means being controlled by said comparison means.

Claim 11

A digital signal processing device as defined in any of claims 1-9, wherein said signal processor is an echo canceller for predicting an echo from a receive signal and subtracting said predicted echo from a send signal, said first digital signal comprising said send signal and said second digital second comprising said receive signal.