Echo canceller for a long-distance telephone network

Claim 2

An echo canceller (100; 200) for use in a long-distance telephone network having a four-wire circuit (120; 120') and a two-wire circuit (3; 3-1 to 3-24), and'responsive to an incoming digital signal supplied from the reception-side path (1) of said four-wire circuit (120; 120') and to an unprocessed digital signal including a digital echo signal supplied to the input of the transmission-side path (2) with an outgoing digital signal substantially free from said digital echo signal, said digital echo signal being inevitably produced at the junction (5; 501 to 524) of the four-wire circuit (120; 120') and the two-wire circuit (3; 3-1 to 3-24), said incoming and outgoing digital signals having mutually different sampling rates, wherein said echo canceller (100; 200) comprises: a) a sample interpolator (10; 20) for converting said incoming digital signal into a digital signal having the same sampling rate as that of the outgoing digital signal on the basis of relative positions of the sampling timings for corresponding imaginary envelopes of the incoming and outgoing digital signals; b) an echo estimator (11; 1101 to 1124) responsive to the output of the sample interpolator (10; 20) for producing an estimated echo signal to cancel said echo signal; and c) means (12; 1201 to 1224) for subtracting the estimated echo signal from the unprocessed digital signal to produce an echo cancelled digital signal.

Claim 3

An echo canceller (100; 200) for use in a long-distance telephone network having a four-wire circuit (120; 120') and a two-wire circuit (3; 3-1 to 3-24), and responsive to an incoming digital signal supplied from the reception-side path (1) of said four-wire circuit (120, 120') and to an unprocessed digital signal including a digital echo signal supplied to the input of the transmission-side path (2) with an outgoing digital signal substantially free from said digital echo signal, said digital echo signal being inevitably produced at the junction (5; 501 to 504) of the four-wire circuit (120, 120') and the two-wire circuit (3; 3-1 to 3-24), said incoming and outgoing digital signals having mutually different sampling rates, wherein said echo canceller (100; 200) comprises: a) a sample interpolator (10; 20) for converting said unprocessed digital signal into a digital signal having the same sampling rate as that of the incoming digital signal oniithe basis of relative positions of the sampling timings for corresponding imaginary envelopes of the incoming and unprocessed digital signals; b) an echo estimator (11; 1101 to 1124) responsive to the output of the sample interpolator (10; 20) for producing an estimated echo signal to cancel said echo signal; and c) means (12; 1201 to 1204) for subtracting the estimated echo signal from the unprocessed digital signal to produce an echo cancelled digital signal.

Claim 4

An echo canceller (100; 200) for use in a long-distance telephone network having a four-wire circuit (120; 120') and a two-wire circuit (3; 3-1 to 3-24), and responsive to an incoming digital signal supplied from the reception-side path (1) of said four-wire circuit (120, 120') and to an unprocessed digital signal including a digital echo signal supplied to the input of the transmission-side path (2) with an outgoing digital signal substantially free from said digital echo signal, said digital echo signal being inevitably produced at the junction (5; 501 to 504) of the four-wire circuit (120, 120') and the two-wire circuit (3; 3-1 to 3-24), said incoming and outgoing digital signals having mutually different sampling rates, wherein said echo canceller (100; 200) comprises: a) a sample interpolator (10; 20) for converting said unprocessed digital signal into a digital signal having the same sampling rate as that of the incoming digital signal oniithe basis of relative positions of the sampling timings for corresponding imaginary envelopes of the incoming and unprocessed digital signals; b) an echo estimator (11; 1101 to 1124) responsive to the output of the sample interpolator (10; 20) for producing an estimated echo signal to cancel said echo signal; and c) means (12; 1201 to 1204) for subtracting the estimated echo signal from the unprocessed digital signal to produce an echo cancelled digital signal.

Claim 5

Device according to claim 1 or 2, characterized in that the sample interpolator (10) comprises a transversal filter (15) having an input terminal for receiving the incoming digital signal through the terminal (6) and an output terminal connected to the estimator (11), a read-only memory (140) for storing the four coefficient groups of the filter (15), and an address generator(130) for generating an address for accessing the ROM (140).

Claim 6

Device according to any of claims 1 to 3, characterized in that the filter (15) comprises three delay elements (1515) to (1517), four multipliers (1510) to (1513), and an adder (1514) for adding up the outputs of the multipliers (1510) to (1513).

Claim 7

Device according to any of claims 1 to 4, characterized in that the generator (130) comprises a counter (1301) and a register (1302), the counter (1301) cleared by a sampling pulse CK2 performing the counting-up operation by a timing pulse 4xCK2 having the repetition cycle four times as fast as that of the sampling pulse CK2, and the register (1302) storing the output of the counter (130) in response to the sampling pulse CK1 to give an upper address for the ROM (140), the lower addresses being fixedly given to the ROM (140) as constant values.

Claim 8

Device according to claim 1 or 2, characterized in that the interpolator (10) comprises a digital filter (15) having a multiplier (151) and an accumulator (152), a coefficient circuit (14) made up of a read-only memory (ROM) for storing the coefficients of the filter (15), a circuit (12) for supplying sample codewords to the digital filter (15), an address generator (13) for producing address for accessing the coefficient circuit (14), and a timing pulse generator (16) for generating pulses to control these circuits (12), (13), and (15).

Claim 9

Device according to claim 6, characterized in that the circuit (12) comprises a register (121) for storing input sample codewords in response to a sampling pulse CK2, a selector (122) for receiving the output of the register (121) at an input terminal B and the output of a shift register (123) at an input terminal A to select either the register (121) or the shift register (123) with a timing pulse CK5, and the four-stage shift register (123) for sequentially shifting the output of the selector (122) in response to timing pulses CK3 and CK4.

Claim 10

Device according to claim 6 or 7, characterized in that the timing pulse generator (16) comprises a part (160) comprising a four-stage shift register (161), an OR gate (162), a delayed-type flip-flop (163), an AND gate (164), and a monostable multivibrator (165) so as to generate timing pulses CK3 and CK4.

Claim 11

Device according to any of claims 1 to 8, characterized in that the echo canceller (200) is designed for 24-channel time division multiplex communication.

Claim 12

Device according to claim 9, characterized in that the interpolator (20) has a 24-channel structure and comprises a register (17), a random access memory (18), a read-address generator (21), a write address generator (20), a selector (19) for switching between these circuits (20) and (21), and another random access memory (22) with an address selector (23).