Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
300 words
An arrangement for simultaneous two-way transmission of data signals with a symbol frequency 1/T over a two-wire circuit having a given bandwidth, said arrangement comprising a one-way transmit channel, a one-way receive channel, a coupler means for interconnecting said channels and the two-wire circuit, an echo canceler comprising an adaptive filter means with adjustable filter coefficients for producing from signals in the transmit channel an approximated echo signal, means for differentially combining said echo signal with signals in the receive channel for forming a residual signal, said filter coefficients being adjustable under the control of the residual signal and the signals in the transmit channel for minimizing a prescribed function of the residual signal, the transmit channel comprising a code converter means for converting p-level data symbols into modified p-level data symbols including means for adding modulo-p the p-level data symbols and modified p-level data symbols which are delayed over a time NT, where N is an integer and means for converting modified p-level data symbols into (2p-1)-level data symbols including means for linearly subtracting said modified p-level data symbols which are delayed over a time NT from the modified p-level data symbols from said adding means, the receive channel comprising an inverse code converter means for converting (2p-1)-level data symbols into p-level data symbols whose levels are equal to the level modulo-p in the (2p-1)-level data symbols, and an extraction circuit means coupled to the receive channel for recovering the symbol frequency from the signals in the receive channel; said adaptive filter comprising a digital adaptive filter having input means for receiving the modified p-level data symbols from the code converter in the transmit channel and signal samples of the residual signal occurring at sampling instants determined by the recovered symbol frequency and means for adjusting the filter coefficients.
Claim 2
Dependent Claim
300 words
An arrangement for simultaneous two-way transmission of data signals with a symbol frequency 1/T over a two-wire circuit having a given bandwidth, said arrangement comprising a one-way transmit channel, a one-way receive channel, a coupler means for interconnecting said channels and the two-wire circuit, an echo canceler comprising an adaptive filter means with adjustable filter coefficients for producing from signals in the transmit channel an approximated echo signal, means for differentially combining said echo signal with signals in the receive channel for forming a residual signal, said filter coefficients being adjustable under the control of the residual signal and the signals in the transmit channel for minimizing a prescribed function of the residual signal, the transmit channel comprising a code converter means for converting p-level data symbols into modified p-level data symbols including means for adding modulo-p the p-level data symbols and modified p-level data symbols which are delayed over a time NT, where N is an integer and means for converting modified p-level data symbols into (2p-1)-level data symbols including means for linearly subtracting said modified p-level data symbols which are delayed over a time NT from the modified p-level data symbols from said adding means, the receive channel comprising an inverse code converter means for converting (2p-1)-level data symbols into p-level data symbols whose levels are equal to the level modulo-p in the (2p-1)-level data symbols, and an extraction circuit means coupled to the receive channel for recovering the symbol frequency from the signals in the receive channel; said adaptive filter comprising a digital adaptive filter having input means for receiving the modified p-level data symbols from the code converter in the transmit channel and signal samples of the residual signal occurring at sampling instants determined by the recovered symbol frequency and means for adjusting the filter coefficients.
Claim 3
Dependent Claim
27 words
An arrangement as claimed in claim 1, wherein said transmit channel further comprises a low pass filter coupled between said code converter means and said coupler means.
Claim 4
Dependent Claim
38 words
An arrangement as claimed in claim 2, wherein said low pass filter comprises a digital filter coupled to said code converter means and a digital to analog converter coupled to said digital filter and to said coupler means.
Claim 5
Dependent Claim
31 words
An arrangement as claimed in claim 1, wherein said receive channel further comprises an inverse code converter coupled to said echo canceler and a regenerator coupled to said inverse code converter.
Claim 6
Dependent Claim
17 words
An arrangement as claimed in claim 4, wherein said inverse code converter comprises a full wave rectifier.
Claim 7
Dependent Claim
17 words
An arrangement as claimed in claim 4, wherein said inverse code converter comprises a sign suppression circuit.
Claim 8
Dependent Claim
21 words
An arrangement as claimed in claim 1, wherein said receive channel further comprises an elastic store coupled to said echo canceler.
Claim 9
Dependent Claim
163 words
An arrangement as claimed in claim 1, wherein said echo canceler comprises a data register; a first switch coupled to said register and to said modulo p adding means; a first multiplier having a first input coupled to said register, a second input, and an output; an accumulator coupled to said output; a first adder having an inverting input coupled to said accumulator, an input coupled to said receive channel, and an output coupled to said receive channel, a second multiplier having inputs coupled to said first adder output and said data register respectively, a second adder coupled to said second multiplier, a second switch coupled to said second adder, a correlation register coupled to said second switch and to said second adder; a third multiplier coupled to said correlation register; a third switch coupled to said third multiplier, a third adder coupled to said third switch and to said first multiplier second input; and a coefficient register coupled to said third adder.