Patent EP0020135A1 successfully refreshed from Google Patents.
EP0020135A1
Expired / Lapsed
EP
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Three-dimensional integration by graphoepitaxy
Assignee: Massachusetts Institute of Technology
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Filing: 1980-05-28
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Granted: —
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Expires: 2000-05-28
Abstract
Abstract The invention relates to a method of making multi-level semi conductor devices which include a first level of devices (12) in the surface of a wafer (11) of semi conductor material and a first film (13) of material deposited on the wafer surface. To produce a further level of devices one or more artificial defects (14) are fabricated in the surface of the first film (13) and a second film (15) of semi conductor material is deposited on the artificial defects so that the crystallographic orientation is influenced by the geometric arrangement of the defect or defects. A second level of semi conductor devices (16) can then be fabricated above the first level in the second film (15).
Inventors
- 👤 Henri I. Smith
- 👤 Dale C. Flanders
- 👤 Michael W. Geis
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 15:24
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/40; H10D62/405; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/32; H10P14/3202; H10P14/3238; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
111 words
A method of making multilevel semiconductor devices which includes the steps of forming a first level of devices (12) in the surface of a wafer (11) of semiconductor material, and depositing a first film (13) of material on the wafer surface, characterized in that one or more artificial defects (14) are fabricated in the surface of the first film (13), and thereafter a second film (15) of semiconductor material is deposited on the artificial defect or defects so that its crystallographic orientation is influenced by the defect or defects (14), and a second level of semi- conductor devices (16) are fabricated, above the first level (12), in the second film (15).
Claim 2
Independent Claim
111 words
A method of making multilevel semiconductor devices which includes the steps of forming a first level of devices (12) in the surface of a wafer (11) of semiconductor material, and depositing a first film (13) of material on the wafer surface, characterized in that one or more artificial defects (14) are fabricated in the surface of the first film (13), and thereafter a second film (15) of semiconductor material is deposited on the artificial defect or defects so that its crystallographic orientation is influenced by the defect or defects (14), and a second level of semi- conductor devices (16) are fabricated, above the first level (12), in the second film (15).
Claim 3
Dependent Claim
17 words
A method according to claim 1, further including conductively interconnecting elements in the first and second levels.
Claim 4
Dependent Claim
85 words
A method according to claim 1 or claim 2, further including the steps of depositing a third film of material on the surface of the second film, fabricating a second set of one or more artificial defects in the surface of the third film, depositing a fourth film of semiconductor material on the second set of defects so that its crystallographic orientation is influenced by the second set and fabricating a further level of semi- conductor devices, above the second level, in the fourth film.
Claim 5
Dependent Claim
21 words
A method according to claim 3, further including the step of conductively interconnecting elements in the first, second and further levels.
Claim 6
Independent Claim
21 words
A method according to any of claims 1 to 4, wherein at least some of the artificial defects comprise point defects.
Claim 7
Independent Claim
22 words
A method according to any of claims 1 to 4, wherein at least some of the artificial defects comrpise surface relief structure.
Claim 8
Dependent Claim
18 words
A multiple level semiconductor device made in accordance with the method of any of claims 1 to 6.
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