CMOS sense amplifier with N-channel sensing

Claim 2

A sense amplifier circuit for a memory device, comprising: a pair of bit lines, and a plurality of memory cells connected to each of said bit lines, a cross-coupled latch circuit including a first pair of N-channel transistors and a second pair of P-channel transistors, each transistor having a source-to-drain path and a gate, the source-to-drain paths of the first pair of N-channel transistor connected between a pair of sense nodes and grounding means, the source-to-drain paths of the second pair of P-channel transistors connected between said sense nodes and a voltage supply node, said grounding means including a third pair of N-channel transistors, each said transistor of the third pair having a source-to-drain path and a gate, said voltage supply node being connected to a positive voltage supply by a source-to-drain path of a second P-channel transistor,

Claim 3

coupling means separately connecting said pair of sense nodes to said pair of bit lines, and control means activating said gate of one of third pair of transistors at a first time in an active cycle when said memory cells are activated for coupling to said bit lines, and then activating said gate of the other of said third pair at a second time when said grounding means is activated, while maintaining said voltage supply node at .[.zero.]. .Iadd.a reference .Iaddend.voltage, .[.then.]. activating after said first time in said operating cycle the gate of said second P-channel transistor.

Claim 4

coupling means separately connecting said pair of sense nodes to said pair of bit lines, and control means activating said gate of one of third pair of transistors at a first time in an active cycle when said memory cells are activated for coupling to said bit lines, and then activating said gate of the other of said third pair at a second time when said grounding means is activated, while maintaining said voltage supply node at .[.zero.]. .Iadd.a reference .Iaddend.voltage, .[.then.]. activating after said first time in said operating cycle the gate of said second P-channel transistor.

Claim 5

A circuit according to claim 1 wherein one of said third pair of N-channel transistors is much smaller than said other of said third pair.

Claim 6

A circuit according to claim 2 wherein said coupling means includes a pair of N-channel coupling transistors .Iadd.selectively coupling said pair of sense nodes to said pair of bit lines.Iaddend..

Claim 7

A circuit according to claim 3 wherein said grounding means including said third pair of N-channel transistors is connected between a grounding node and a Vss terminal of a voltage supply.

Claim 8

A circuit according to claim 4 wherein said control means activates the .[.gates.]. .Iadd.gate of one .Iaddend.of said third pair of N-channel transistors and said second P-channel transistor .Iadd.with a control signal and an inverted signal derived from said control signal.Iaddend..

Claim 9

A circuit according to claim 5 wherein said memory cells are one-transistor dynamic MOS read/write memory cells.

Claim 10

A CMOS sense amplifier circuit for a semiconductor memory array, the array having row lines for selecting cells based on an address, and having bit lines perpendicular to the row lines and connected to the cells, comprising: a CMOS bistable latch circuit having differential inputs, and having first and second power supply nodes, each of the differential inputs being coupled to one of said bit lines for sensing the voltage thereon;

Claim 11

A CMOS sense amplifier circuit for a semiconductor memory array, the array having row lines for selecting cells based on an address, and having bit lines perpendicular to the row lines and connected to the cells, comprising: a CMOS bistable latch circuit having differential inputs, and having first and second power supply nodes, each of the differential inputs being coupled to one of said bit lines for sensing the voltage thereon;

Claim 12

the bistable latch circuit including a pair of matched cross-coupled N-channel driver transistors with each driver transistor having a source-drain path connected between said first power supply node and one of the differential inputs, and the bistable latch circuit having a pair of cross-coupled P-channel transistors having a source-drain path connected between said second power supply node and one of the differential inputs; first and second N-channel transistors having gates, and having source-to-drain paths connected in parallel between said first power supply node and a reference terminal of a power supply, said first transistor being of high resistance and having its gate connected to a first clock voltage, .[.said second transistor being of low resistance and having its gate connected to a first clock voltage,.]. said second transistor being of low resistance and having its gate connected to a second clock voltage, a third P-channel transistor having a gate and having a source-to-drain path connected between said second power supply node and a positive terminal of said power supply, said third transistor being of high resistance and having its gate connected to a complement of said second clock voltage, clock means applying said first clock voltage to the gate of said first transistor at a given time in an operating cycle, and thereafter applying said second clock voltage to the gate of said second transistor and applying said complement of said second clock voltage to said third transistor later in such operating cycle; said second power supply node being maintained at substantially the voltage of .[.said.]. .Iadd.a .Iaddend.reference .[.terminal.]. .Iadd.level .Iaddend.in said operating cycle until said later time.

Claim 13

the bistable latch circuit including a pair of matched cross-coupled N-channel driver transistors with each driver transistor having a source-drain path connected between said first power supply node and one of the differential inputs, and the bistable latch circuit having a pair of cross-coupled P-channel transistors having a source-drain path connected between said second power supply node and one of the differential inputs; first and second N-channel transistors having gates, and having source-to-drain paths connected in parallel between said first power supply node and a reference terminal of a power supply, said first transistor being of high resistance and having its gate connected to a first clock voltage, .[.said second transistor being of low resistance and having its gate connected to a first clock voltage,.]. said second transistor being of low resistance and having its gate connected to a second clock voltage, a third P-channel transistor having a gate and having a source-to-drain path connected between said second power supply node and a positive terminal of said power supply, said third transistor being of high resistance and having its gate connected to a complement of said second clock voltage, clock means applying said first clock voltage to the gate of said first transistor at a given time in an operating cycle, and thereafter applying said second clock voltage to the gate of said second transistor and applying said complement of said second clock voltage to said third transistor later in such operating cycle; said second power supply node being maintained at substantially the voltage of .[.said.]. .Iadd.a .Iaddend.reference .[.terminal.]. .Iadd.level .Iaddend.in said operating cycle until said later time.

Claim 14

A circuit according to claim 7 wherein said pair of cross-coupled P-channel transistors have source-to-drain paths separately connecting said differential inputs to said second power supply node.

Claim 15

A circuit according to claim 8 wherein applying only said first and third clock voltages produces a slow sensing operation; and applying said first, second and third clock voltages produces a fast sensing operation.

Claim 16

A circuit according to claim 8 wherein said cells are one-transistor dynamic memory cells.

Claim 17

A semiconductor memory device containing an array of rows and columns of memory cells including row lines for selecting cells based on an address, and including bit lines perpendicular to the row lines and connected to the cells; said device comprising: (a) a plurality of sense amplifiers, each sense amplifier including a bistable CMOS latch circuit having a pair of sense nodes providing differential inputs, and having a positive supply node and a grounding node, each of the differential inputs being coupled to one of said bit lines for sensing the voltage thereon; said bistable latch circuit including a pair of N-channel transistor having a source-to-drain paths separately connecting said sense nodes to said grounding node, and including a pair of P-channel transistors having source-to-drain paths separately connecting said sense nodes to said supply node; (b) first and second N-channel .[.transistor shaving.]. .Iadd.transistors sharing .Iaddend.gates, and having source-to-drain paths separately connected in parallel between said grounding node and a ground terminal of a power supply, said first N-channel transistor being of high resistance and having its gate connected to a first clock voltage, said second N-channel transistor being of low resistance and having its gate connected to a second clock voltage, (c) a third P-channel transistor having a gate and having a source-to-drain path connected between said positive supply node and the positive voltage terminal of said power supply, said third transistor being of high resistance and having its gate connected to a third clock voltage, said positive supply node being maintained at about the voltage of .[.said ground terminal.]. .Iadd.a reference level .Iaddend.until said gate of the third P-channel transistor is activated; (d) clock means applying said first clock voltage to the gate of said first transistor at a given time in an operating cycle, and thereafter applying said second clock and said third clock voltages to the gates of said second and third transistors later in such operating cycle.

Claim 18

A semiconductor memory device containing an array of rows and columns of memory cells including row lines for selecting cells based on an address, and including bit lines perpendicular to the row lines and connected to the cells; said device comprising: (a) a plurality of sense amplifiers, each sense amplifier including a bistable CMOS latch circuit having a pair of sense nodes providing differential inputs, and having a positive supply node and a grounding node, each of the differential inputs being coupled to one of said bit lines for sensing the voltage thereon; said bistable latch circuit including a pair of N-channel transistor having a source-to-drain paths separately connecting said sense nodes to said grounding node, and including a pair of P-channel transistors having source-to-drain paths separately connecting said sense nodes to said supply node; (b) first and second N-channel .[.transistor shaving.]. .Iadd.transistors sharing .Iaddend.gates, and having source-to-drain paths separately connected in parallel between said grounding node and a ground terminal of a power supply, said first N-channel transistor being of high resistance and having its gate connected to a first clock voltage, said second N-channel transistor being of low resistance and having its gate connected to a second clock voltage, (c) a third P-channel transistor having a gate and having a source-to-drain path connected between said positive supply node and the positive voltage terminal of said power supply, said third transistor being of high resistance and having its gate connected to a third clock voltage, said positive supply node being maintained at about the voltage of .[.said ground terminal.]. .Iadd.a reference level .Iaddend.until said gate of the third P-channel transistor is activated; (d) clock means applying said first clock voltage to the gate of said first transistor at a given time in an operating cycle, and thereafter applying said second clock and said third clock voltages to the gates of said second and third transistors later in such operating cycle.

Claim 19

A device according to claim 11 wherein said third clock voltage is the complement of said second clock voltage.

Claim 20

A device according to claim 11 wherein said memory cells are one-transistor dynamic memory cells.

Claim 21

A device according to claim 13 including a pair of coupling transistors separately connecting said sense nodes to said bit lines.

Claim 22

A device according to claim 11 wherein the gain of said third P-channel transistor is less than that of said second N-channel transistor. .Iadd.

Claim 23

A circuit according to claim 1 wherein said reference voltage is about one-half the voltage of said voltage supply node. .Iaddend. .Iadd.17. A circuit according to claim 7 wherein the voltage of said reference level is about one-half the voltage of said positive terminal of said power supply. .Iaddend. .Iadd.18. A device according to claim 11 wherein said reference voltage is about one-half the voltage of said positive voltage terminal. .Iaddend. .Iadd.19. A circuit according to claim 3 wherein said pair of N-channel coupling transistors are turned on at said first and second times but turned off prior to said first time in said active operating cycle. .Iaddend. .Iadd.20. A device according to claim 14 wherein said pair of coupling transistors are turned off prior to said given time in an operating cycle and turned on when said first, second and third clock voltages occur. .Iaddend.