US4551641A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense amplifier
Assignee: Motorola Solutions Inc
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Filing: 1983-11-23
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Granted: 1985-11-05
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Expires: 2003-11-23
Abstract
Abstract A sense amplifier is coupled to a pair of bit lines for detecting and amplifying a voltage differential therebetween. The sense amplifier has a first differential amplifier coupled to the pair of bit lines enabled in response to a first signal. The sense amplifier also has a second differential amplifier coupled to the pair of bit lines which is enabled a predetermined time duration following the occurrence of the first signal.
Inventors
- 👤 Perry H. Pelley, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/06; G11C7/065; G11C11/409; G11C11/4091; H; H03; H03F; H03F3/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
355 words
A sense amplifier coupled to a pair of bit lines for sensing and amplifying a voltage differential between the pair of bit lines, comprising: a first n channel transistor having a first current electrode coupled to a first bit line of the pair of bit lines, a control electrode coupled to a second bit line of the pair of bit lines, and a second current electrode; a second n channel transistor having a first current electrode coupled to the second bit line, a control electrode coupled to the first bit line, and a second current electrode coupled to the second current electrode of the first transistor; a third n channel transistor having a first current electrode coupled to the second current electrodes of the first and second n channel transistors, a control electrode for receiving a first signal, and a second current electrode coupled to a first power supply terminal; a first p channel transistor having a first current electrode coupled to the first bit line, a control electrode coupled to the second bit line, and a second current electrode; a second p channel transistor having a first current electrode coupled to the second bit line, a control electrode coupled to the first bit line, and a second current electrode coupled to the second current electrode of the first p channel transistor; a third p channel transistor having a first current electrode coupled to the second current electrodes of the first and second p channel transistors, a control electrode for receiving a second signal, and a second current electrode coupled to a second power supply terminal; and a fourth n channel transistor having a first current electrode coupled to the second current electrodes of the first and second n channel transistors, a control electrode for receiving a third signal, and a second current electrode coupled to the first power supply terminal; wherein the second signal switches to a logic low a predetermined time duration after the first signal switches to a logic high, and the third signal switches to a logic high a predetermined time duration after the second signal switches to a logic low.
Claim 2
Dependent Claim
355 words
A sense amplifier coupled to a pair of bit lines for sensing and amplifying a voltage differential between the pair of bit lines, comprising: a first n channel transistor having a first current electrode coupled to a first bit line of the pair of bit lines, a control electrode coupled to a second bit line of the pair of bit lines, and a second current electrode; a second n channel transistor having a first current electrode coupled to the second bit line, a control electrode coupled to the first bit line, and a second current electrode coupled to the second current electrode of the first transistor; a third n channel transistor having a first current electrode coupled to the second current electrodes of the first and second n channel transistors, a control electrode for receiving a first signal, and a second current electrode coupled to a first power supply terminal; a first p channel transistor having a first current electrode coupled to the first bit line, a control electrode coupled to the second bit line, and a second current electrode; a second p channel transistor having a first current electrode coupled to the second bit line, a control electrode coupled to the first bit line, and a second current electrode coupled to the second current electrode of the first p channel transistor; a third p channel transistor having a first current electrode coupled to the second current electrodes of the first and second p channel transistors, a control electrode for receiving a second signal, and a second current electrode coupled to a second power supply terminal; and a fourth n channel transistor having a first current electrode coupled to the second current electrodes of the first and second n channel transistors, a control electrode for receiving a third signal, and a second current electrode coupled to the first power supply terminal; wherein the second signal switches to a logic low a predetermined time duration after the first signal switches to a logic high, and the third signal switches to a logic high a predetermined time duration after the second signal switches to a logic low.
Claim 3
Dependent Claim
66 words
The sense amplifier of claim 1 wherein the third p channel transistor, the third n channel transistor, and the fourth n channel transistor each have a gain, the gain of the fourth n channel transistor being greater than the gain of the third p channel transistor, and the gain of the third p channel transistor being greater than the gain of the third n channel transistor.
Claim 4
Dependent Claim
43 words
The sense amplifier of claim 2 further comprising a fifth n channel transistor having a first current electrode coupled to the first bit line, a second current electrode coupled to the second bit line, and a control electrode for receiving a fourth signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-04 | 1989-05-06 | 1989-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-04 | 1993-05-06 | 1993-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-04 | 1997-05-06 | 1997-11-05 | $7700.00 | Window Closed / Lapsed |