Patent USRE33332E successfully refreshed from Google Patents.
USRE33332E
Expired / Lapsed
US
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Apparatus for correcting errors
Assignee: Sony Corp
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Filing: 1988-11-14
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Granted: 1990-09-11
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Expires: 2008-11-14
Abstract
Abstract There is provided an apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to the processing for the error correction coding when data consisting of different kinds of n symbols and m symbols is transmitted as a unit. This error correcting apparatus comprises: a first decoder to which (n+k) symbols are supplied and which generates a first flag signal indicative of the error state by at least performing the error detection; and a second decoder to which the (n+k) symbols corrected by the first decoder and the (m+l) symbols received are supplied and which generates a second flag signal representing the error state by performing the error detection and performs the error correction using the first and second flag signals.
Inventors
- 👤 Tsuneo Furuya
- 👤 Katsuya Hori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:40
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
280 words
An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having different kinds of information and l parity symbols is transmitted as a unit, said processing consisting of an encoding process with respect to a first error detection code or an error correction code for generating a redundancy code of k symbols regarding said n symbols, and an encoding process with respect to a second error correction code for generating a redundancy code of .[.one symbol.]. .Iadd.1 symbols .Iaddend.regarding (n+k+m) symbols, wherein said error correcting apparatus comprising: a first decoder with respect to said first error detection code or said error correction code to which said redundancy code of (n+k) symbols is supplied and which generates a first flag signal indicative of the error state by at least performing the error detection wherein said first flag signal is the signal indicating the number (including 0) of error symbols with respect to the (n+k) symbols; and a second .[.decorder.]. .Iadd.decoder .Iaddend.with respect to said second error correction code to which (n+k) symbols corrected by said first decoder and (m+1) symbols received are supplied and which generates a second flag signal representing the error state by performing the error detection, wherein said second flag signal is the signal representing the number (including 0) of error symbols before the error correction by said second decoder with respect to the (n+k+m+l) symbols, and performs the error correction by comparing said first and second flag signals and the error correction processing by said second decoder is controlled in accordance with the result of said comparison.
Claim 2
Independent Claim
280 words
An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having different kinds of information and l parity symbols is transmitted as a unit, said processing consisting of an encoding process with respect to a first error detection code or an error correction code for generating a redundancy code of k symbols regarding said n symbols, and an encoding process with respect to a second error correction code for generating a redundancy code of .[.one symbol.]. .Iadd.1 symbols .Iaddend.regarding (n+k+m) symbols, wherein said error correcting apparatus comprising: a first decoder with respect to said first error detection code or said error correction code to which said redundancy code of (n+k) symbols is supplied and which generates a first flag signal indicative of the error state by at least performing the error detection wherein said first flag signal is the signal indicating the number (including 0) of error symbols with respect to the (n+k) symbols; and a second .[.decorder.]. .Iadd.decoder .Iaddend.with respect to said second error correction code to which (n+k) symbols corrected by said first decoder and (m+1) symbols received are supplied and which generates a second flag signal representing the error state by performing the error detection, wherein said second flag signal is the signal representing the number (including 0) of error symbols before the error correction by said second decoder with respect to the (n+k+m+l) symbols, and performs the error correction by comparing said first and second flag signals and the error correction processing by said second decoder is controlled in accordance with the result of said comparison.
Claim 3
Dependent Claim
64 words
An error correcting apparatus according to claim 1, wherein said (n+k+m+l) symbols are the data which is recorded as the subchannel of a disc on which an information signal was recorded as the main channel, and said m symbols are the data for display in the data in said subchannel or the audio data, and n symbols are the control data from said subchannel.
Claim 4
Independent Claim
245 words
An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having .[.difference.]. .Iadd.different .Iaddend.kinds of information and l parity symbols is transmitted as a unit, said processing consisting of an encoding process with respect to a first error correction code for generating a redundancy code of k symbols regarding said n symbols, and n encoding process with respect to a second error correction code for generating a redundancy code of .[.one symbol.]. .Iadd.l symbols .Iaddend.regarding (n+k+m) symbols, wherein said error correcting apparatus comprising: a first decoder with respect to said second error correction code to which said (n+k+m+l) symbols are supplied and which generates a first flag signal indicative of the number (including 0) of error symbols and the error locations by performing the error detection regarding the (n+k+m+l) symbols and performs the error correction regarding the (m+l) symbols; a second decoder with respect to said first error correction code to which (n+k) symbols transmitted through said first decoder are supplied and which generates a second flag signal representing the number (including 0) of error symbols and performs the error correction .[.suing.]. .Iadd.using .Iaddend.said first and second flag signals; and a third decoder with respective to said second error correction code to which the (n+k+m+l) symbols are supplied from said first and second decoders and which performs the error correction using said second flag signal.
Claim 5
Independent Claim
245 words
An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having .[.difference.]. .Iadd.different .Iaddend.kinds of information and l parity symbols is transmitted as a unit, said processing consisting of an encoding process with respect to a first error correction code for generating a redundancy code of k symbols regarding said n symbols, and n encoding process with respect to a second error correction code for generating a redundancy code of .[.one symbol.]. .Iadd.l symbols .Iaddend.regarding (n+k+m) symbols, wherein said error correcting apparatus comprising: a first decoder with respect to said second error correction code to which said (n+k+m+l) symbols are supplied and which generates a first flag signal indicative of the number (including 0) of error symbols and the error locations by performing the error detection regarding the (n+k+m+l) symbols and performs the error correction regarding the (m+l) symbols; a second decoder with respect to said first error correction code to which (n+k) symbols transmitted through said first decoder are supplied and which generates a second flag signal representing the number (including 0) of error symbols and performs the error correction .[.suing.]. .Iadd.using .Iaddend.said first and second flag signals; and a third decoder with respective to said second error correction code to which the (n+k+m+l) symbols are supplied from said first and second decoders and which performs the error correction using said second flag signal.
Claim 6
Dependent Claim
65 words
An error correcting apparatus according to claim 3, wherein said (n+k+m+l) symbols are the data which is recorded as the subchannel of a disc on which an information signal was recorded as the main channel, and said m symbols are the data for display in the data in said subchannel or the audio data, and said n symbols are the control data for said subchannel.
Claim 7
Dependent Claim
321 words
An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having different kinds of information and l parity symbols is transmitted as a unit, said processing consisting of: an encoding process with respect to a first error detection code or an error correction code for generating a redundancy code of k symbols regarding said n symbols, and an encoding process with respect to a second error correction code for generating a redundancy code of .[.one symbol.]. l symbols regarding (n+k+m) symbols, wherein said error correcting apparatus comprises: a first decoder with respect to said first error detection code or said error correction code to which said redundancy code of (n+k) symbols is supplied and which generates a first flag signal indicative of the error state by at least performing the error detection wherein said first flag signal is the signal indicating the number (including .Badd.0) of error symbols with respect to the (n+k) symbols; and a second decoder with respect to said second error correction code to which (n+k) symbols corrected by said first decoder and (m+l) symbols received are supplied and which generates a second flag signal representing the error state by performing the error detection, wherein said second flag signal is the signal representing the error locations among the (n+k+m+l) symbols before the error correction by said second decoder, and performs the error correction by comparing said first and second flag signals and the error correction processing by said second decoder is controlled in accordance with the result of said comparison. .Iadd.6. An error correcting apparatus according to claim 1, wherein l equals four parity symbols. .Iaddend. .Iadd.7. An error correcting apparatus according to claim 3, wherein l equals four parity symbols. .Iaddend. .Iadd.8. An error correcting apparatus according to claim 5, wherein l equals four parity symbols. .Iaddend.
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