Circuit arrangement for monitoring speed of a drive motor

Claim 2

Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of the input signal sequence, and an evaluation circuit having at least one threshold value means responsive to the output signal for providing an alarm signal when the amplitude of the output signal reaches a value corresponding to a drop of the motor speed below a predetermined minimum speed, said evaluation circuit having a predetermined response delay exceeding the acceleration time of the motor to prevent provision of said alarm signal during motor start-up.

Claim 3

Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means responsive to said output signal for providing an alarm signal when the amplitude of said output signal reaches a value corresponding to an increase of the motor speed above a predetermined maximum speed, said evaluation circuit having a predetermined delay exceeding the acceleration time of said motor to prevent the provision of said alarm signal during starting of said motor.

Claim 4

Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means responsive to said output signal for providing an alarm signal when the amplitude of said output signal reaches a value corresponding to an increase of the motor speed above a predetermined maximum speed, said evaluation circuit having a predetermined delay exceeding the acceleration time of said motor to prevent the provision of said alarm signal during starting of said motor.

Claim 5

A circuit arrangement according to claim 1 or 2, wherein the detection means comprises a pulse shaping stage for producing a rectangular pulse train defining said input signal sequence.

Claim 6

A circuit arrangement according to claim 2, wherein the signal converter includes a differentiating stage coupled between the detection means and the output of the signal converter.

Claim 7

A circuit arrangement according to claim 4, wherein the signal converter is provided with a first charge storage chargeable through a charging path and with switching means coupled to said charge storage for discharging said charge storage, said switching means being triggered by output signals from the differentiating stage.

Claim 8

A circuit arrangement according to claim 5, wherein the charging time constant of the charge storage is a multiple of the discharging time constant thereof.

Claim 9

A circuit arrangement according to claim 6, wherein the charge storage is connected in the input circuit of a first threshold value stage of said signal converter.

Claim 10

A circuit arrangement according to claim 7, wherein the first threshold value stage is designed to supply output pulses of constant amplitude, the pulse width of said output pulses being a function of the length of time when the voltage across said first charge storage exceeds a predetermined threshold value, and wherein said signal converter further comprises integrator means for integrating the output pulses of the first threshold value stage.

Claim 11

A circuit arrangement according to claim 7, wherein a second charge storage chargeable through a further charging path from a d.c. voltage source is discharged by means of the first threshold value stage during the time intervals when the voltage across the first charge storage exceeds a predetermined threshold value.

Claim 12

A circuit arrangement according to claim 1 or 2, wherein an RC delay circuit and further threshold value means connected to the output thereof are connected to the output of said at least one threshold value means for suppressing the detection of brief drops below a predetermined speed to be monitored.

Claim 13

A circuit arrangement according to claim 1 or 2, further comprising an RC element with resistance means connected between the output of the signal converter and the signal input of the threshold value means and a capacitor connected on one terminal with the signal input of the threshold value means, whereby only after said capacitor connected on one terminal with the signal input has been charged to a predetermined value is the threshold value means responsive to an input signal thereto.

Claim 14

A circuit arrangement according to claim 1 or 2, wherein the threshold value means is provided with positive feedback from the output thereof.

Claim 15

A circuit arrangement according to claim 11 wherein the other terminal of the capacitor is subject to the action of part of the output signal of the threshold value means.

Claim 16

A circuit arrangement according to claim 1 or 2, wherein the evaluation circuit has a latch function.

Claim 17

A circuit arrangement according to claim 14, wherein a storage means is provided for executing said latch function by storing said alarm signal.

Claim 18

A circuit arrangement according to claim 15, wherein said storage means comprises a resettable digital storage device.

Claim 19

A circuit arrangement according to claim 16, wherein the resettable digital storage device has a comparator with feed-back means by which the comparator is locked in the set state following setting and is adapted to be unlocked by external action only.

Claim 20

A circuit arrangement according to claim 17, wherein the feed-back means of said digital storage device is connected to an input of the threshold value means for also locking said threshold value means in response to said alarm signal.

Claim 21

A circuit arrangement according to claim 15, wherein the threshold value means is itself constructed as the storage means.

Claim 22

A circuit arrangement according to claim 19, wherein said threshold value means has associated thereto locking means which can only be unlocked by external action.

Claim 23

A circuit arrangement according to claim 20, wherein a diode is connected between the outputs of the signal converter and the threshold value means.

Claim 24

A circuit arrangement according to claim 1 or 2, wherein its power supply is insulated from the power supply of the motor.

Claim 25

A circuit arrangement according to claim 22, wherein the evaluation circuit is connected to the output of the signal converter via an optoelectronic coupler.

Claim 26

A circuit arrangement according to claim 3, wherein the active components of the pulse shaping stage, the signal converter and the evaluation circuit are formed by an integrated quadruple comparator circuit.

Claim 27

A circuit arrangement according to claim 1 or 2, wherein the detection device has a sensor coil which is positioned as an additional winding on at least one stator pole of an electric motor to be monitored.

Claim 28

A circuit arrangement according to claim 1 or 2, wherein the detection device has a sensor coil with an associated sensor magnet disposed such that a ferromagnetic part of the motor to be monitored moves past it.

Claim 29

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having a predetermined response delay, said evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to a drop of the monitored speed below a predetermined minimum speed, and an RC circuit including resistance means connected between the output of the signal converter and the signal input of said threshold value means and a capacitor, one terminal of said capacitor being connected with the signal input of said threshold value means and the other terminal of said capacitor being subject to the action of part of the output signal of said threshold value means, whereby said threshold value means is prevented from responding to an input signal applied thereto until the voltage across said capacitor exceeds a predetermined value thereby to provide for said response delay.

Claim 30

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having a predetermined response delay, said evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to a drop of the monitored speed below a predetermined minimum speed, and an RC circuit including resistance means connected between the output of the signal converter and the signal input of said threshold value means and a capacitor, one terminal of said capacitor being connected with the signal input of said threshold value means and the other terminal of said capacitor being subject to the action of part of the output signal of said threshold value means, whereby said threshold value means is prevented from responding to an input signal applied thereto until the voltage across said capacitor exceeds a predetermined value thereby to provide for said response delay.

Claim 31

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means which is responsive to said output signal and which responds by providing a recognition signal if the amplitude of said output signal reaches a value corresponding to a drop below a predetermined minimum speed, said evaluation circuit having a latch function for said recognition signal.

Claim 32

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means which is responsive to said output signal and which responds by providing a recognition signal if the amplitude of said output signal reaches a value corresponding to a drop below a predetermined minimum speed, said evaluation circuit having a latch function for said recognition signal.

Claim 33

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to a drop of the monitored speed below a predetermined minimum speed, said evaluation circuit being provided with its own power supply.

Claim 34

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to a drop of the monitored speed below a predetermined minimum speed, said evaluation circuit being provided with its own power supply.

Claim 35

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having a predetermined response delay, said evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to an increase of the monitored speed over a predetermined maximum speed, and an RC circuit including resistance means connected between the output of the signal converter and the signal input of said threshold value means and a capacitor, one terminal of said capacitor being connected with the signal input of said threshold value means and the other terminal of said capacitor being subject to the action of part of the output signal of said threshold value means, whereby said threshold value means is prevented from responding to an input signal applied thereto until the voltage across said capacitor exceeds a predetermined value thereby to provide for said response delay.

Claim 36

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having a predetermined response delay, said evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to an increase of the monitored speed over a predetermined maximum speed, and an RC circuit including resistance means connected between the output of the signal converter and the signal input of said threshold value means and a capacitor, one terminal of said capacitor being connected with the signal input of said threshold value means and the other terminal of said capacitor being subject to the action of part of the output signal of said threshold value means, whereby said threshold value means is prevented from responding to an input signal applied thereto until the voltage across said capacitor exceeds a predetermined value thereby to provide for said response delay.

Claim 37

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means which is responsive to said output signal and which responds by providing a recognition signal if the amplitude of said output signal reaches a value corresponding to an increase over a predetermined maximum speed, said evaluation circuit having a latch function for said recognition signal.

Claim 38

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having at least one threshold value means which is responsive to said output signal and which responds by providing a recognition signal if the amplitude of said output signal reaches a value corresponding to an increase over a predetermined maximum speed, said evaluation circuit having a latch function for said recognition signal.

Claim 39

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to an increase of the monitored speed over a predetermined maximum speed, said evaluation circuit being provided with its own power supply. .Iadd.

Claim 40

A circuit arrangement for speed monitoring, particularly for fan drives, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal the amplitude of which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit including at least one threshold value means which is responsive to said output signal and which responds if the amplitude of said output signal reaches a value corresponding to an increase of the monitored speed over a predetermined maximum speed, said evaluation circuit being provided with its own power supply. .Iadd.

Claim 41

Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal which is a function of the repetition frequency of the input signal sequence, and an evaluation circuit having means responsive to the output signal for providing an alarm signal when the output signal corresponds to a drop of the motor speed below a predetermined minimum speed, said evaluation circuit having a predetermined response delay exceeding the acceleration time of the motor to prevent provision of said alarm signal during motor start-up. .Iaddend. .Iadd.34. Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having means responsive to said output signal for providing an alarm signal when said output signal corresponds to an increase of the motor speed above a predetermined maximum speed, said evaluation circuit having a predetermined delay exceeding the acceleration time of said motor to prevent the provision of said alarm signal during starting of said motor. .Iaddend.

Claim 42

Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal which is a function of the repetition frequency of the input signal sequence, and an evaluation circuit having means responsive to the output signal for providing an alarm signal when the output signal corresponds to a drop of the motor speed below a predetermined minimum speed, said evaluation circuit having a predetermined response delay exceeding the acceleration time of the motor to prevent provision of said alarm signal during motor start-up. .Iaddend. .Iadd.34. Circuit arrangement for monitoring the speed of a drive motor, comprising detection means for producing an input signal sequence having a speed-dependent repetition frequency, a signal converter for converting the input signal sequence into an output signal which is a function of the repetition frequency of said input signal sequence, and an evaluation circuit having means responsive to said output signal for providing an alarm signal when said output signal corresponds to an increase of the motor speed above a predetermined maximum speed, said evaluation circuit having a predetermined delay exceeding the acceleration time of said motor to prevent the provision of said alarm signal during starting of said motor. .Iaddend.