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Field-effect transistor

Assignee: United States Department of the Navy
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Filing: 1980-09-16
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Granted: 1987-11-03
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Expires: 2000-09-16
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Abstract

Abstract A method of improving field-effect transistors, and the product thereof, wherein the resistivity of the upper layer of the source-gate channel region of a GaAs field-effect transistor (FET) may be selectively raised is disclosed. Impurity ions are implanted in the source-gate channel region followed by a much shallower implantation of boron in the same region. The boron ion concentration should exceed the N+ impurity ion concentration by a factor of 2 or more.

Inventors

  • 👤 Max N. Yoder

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 17:13
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/206; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/328; H10P30/208

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 214 words
An improved field-effect transistor of the type having a semi-insulating GsAs substrate, an active layer ion implanted into said semi-insulating GaAs substrate, a source fashioned on one end of said semi-insulating GaAs substrate, a drain fashioned on the other end thereof and a Schottky barrier gate fashioned therebetween, said source, said drain and said Schottky barrier gate being fashioned contiguous to the top of said active layer so as to define a first active region underlying said source, a second active region lying between said source and said Schottky barrier gate, a third active region having a portion underlying said Schottky barrier gate and a portion lying between said Schottky barrier gate and said drain, and a fourth active region underlying said drain, wherein the improvement comprises: selectively implanting said semi-insulating GaAs substrate with impurity ions to the N+ state to form said first, second and fourth active regions, and implanting said semi-insulating GaAs substrate with said impurity ions to the N state to form said third active region; and selectively implanting a top portion of said second active region to a predetermined depth with a predetermined concentration of boron ions so as to raise the resistivity of said top portion thereof, said top portion extending from said source to said Schottky barrier gate.
Claim 2
Dependent Claim 214 words
An improved field-effect transistor of the type having a semi-insulating GsAs substrate, an active layer ion implanted into said semi-insulating GaAs substrate, a source fashioned on one end of said semi-insulating GaAs substrate, a drain fashioned on the other end thereof and a Schottky barrier gate fashioned therebetween, said source, said drain and said Schottky barrier gate being fashioned contiguous to the top of said active layer so as to define a first active region underlying said source, a second active region lying between said source and said Schottky barrier gate, a third active region having a portion underlying said Schottky barrier gate and a portion lying between said Schottky barrier gate and said drain, and a fourth active region underlying said drain, wherein the improvement comprises: selectively implanting said semi-insulating GaAs substrate with impurity ions to the N+ state to form said first, second and fourth active regions, and implanting said semi-insulating GaAs substrate with said impurity ions to the N state to form said third active region; and selectively implanting a top portion of said second active region to a predetermined depth with a predetermined concentration of boron ions so as to raise the resistivity of said top portion thereof, said top portion extending from said source to said Schottky barrier gate.
Claim 3
Dependent Claim 36 words
The improved field-effect transistor of claim 1 wherein the N state corresponds to a concentration of approximately 1×10 17 /cm 3 and the N+ state corresponds to a concentration of approximately 1×10 18 /cm 3 .
Claim 4
Dependent Claim 42 words
The improved field-effect transistor of claim 2 wherein the predetermined concentration of boron ions is at least two times the concentration of the N+ state but less than that which cause said top portion of said second active region to become amorphous.
Claim 5
Dependent Claim 22 words
The improved field-effect transistor of claim 3 wherein the predetermined depth of said top portion is in the range of 200-500 Å.
Claim 6
Dependent Claim 26 words
The improved field-effect transistor of claim 4 wherein said impurity ions are selected from the group consisting of Si and a mixture of Si and S.

References Cited (Backward Citations)

US3804681A Cited
US3997908A Cited
US4196439A Cited
US4244097A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-11-02 1991-05-04 1991-11-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-11-02 1995-05-04 1995-11-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-11-02 1999-05-04 1999-11-03 $7700.00 Window Closed / Lapsed

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