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USH1222H
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Apparatus for determining sticky bit value in arithmetic operations
Assignee: International Business Machines Corp
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Filing: 1991-12-30
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Granted: 1993-08-03
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Expires: 2011-12-30
Abstract
Abstract An apparatus for determining the correct value to be assigned to the "sticky-bit" (S) position as a consequence of an arithmetic floating point multiply, divide or square root operation. The apparatus measures the number of trailing zeroes in the operand registers, performs a sum or difference calculation of these values, and compares the result with a third value to determine the sticky-bit value.
Inventors
- 👤 Jeffrey D. Brown
- 👤 Roy R. Faget
- 👤 Scott A. Hilker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:26
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/499; G06F7/49942; G06F7/49947; G06F7/49952
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
226 words
An apparatus for determining the sticky bit value as the result of a floating point divide operation in a binary computer processor, comprising: a) a first register means for holding the dividend fraction, and a second register means for holding the divisor fraction; b) a first and second trailing zero detector circuit respectively connected to each of said first and second register means, including means for providing an output representing the number of trailing zeroes in said register means; c) a subtractor circuit connected to said trailing zero detector circuits said subtracter circuit having an output representative of the difference between the number of trailing zeroes in said respective register means; d) a comparator circuit having a first input connected to receive said subtractor circuit output, and having a second input; e) a quotient fraction register means for storing the quotient resulting from a division calculation of said dividend fraction and said divisor fraction; f) a third trailing zero detector circuit connected to said quotient fraction register, including means for providing an output representing the number of quotient fraction trailing zeroes; said output being connected to the second input of said comparator, said comparator having an output for producing a sticky bit "1" value when said first and second inputs are unequal and a sticky bit "0" value when said first and second inputs are equal.
Claim 2
Independent Claim
226 words
An apparatus for determining the sticky bit value as the result of a floating point divide operation in a binary computer processor, comprising: a) a first register means for holding the dividend fraction, and a second register means for holding the divisor fraction; b) a first and second trailing zero detector circuit respectively connected to each of said first and second register means, including means for providing an output representing the number of trailing zeroes in said register means; c) a subtractor circuit connected to said trailing zero detector circuits said subtracter circuit having an output representative of the difference between the number of trailing zeroes in said respective register means; d) a comparator circuit having a first input connected to receive said subtractor circuit output, and having a second input; e) a quotient fraction register means for storing the quotient resulting from a division calculation of said dividend fraction and said divisor fraction; f) a third trailing zero detector circuit connected to said quotient fraction register, including means for providing an output representing the number of quotient fraction trailing zeroes; said output being connected to the second input of said comparator, said comparator having an output for producing a sticky bit "1" value when said first and second inputs are unequal and a sticky bit "0" value when said first and second inputs are equal.
Claim 3
Dependent Claim
33 words
The apparatus of claim 1, wherein said subtracter circuit further comprises an output representative of the difference between the number of trailing zeroes in said respective register means, modified by a constant value.
Claim 4
Dependent Claim
81 words
The apparatus of claim 1, wherein said comparator further comprises means for generating a first output signal when said number of trailing zeroes in said quotient register is equal to the difference of the number of trailing zeroes in said first and second register means, and means for generating a second output signal when said number of trailing zeroes in said quotient register is unequal to the difference of the number of trailing zeroes in said first and second register means.
Claim 5
Dependent Claim
18 words
The apparatus of claim 1, wherein the first and second register means further comprises a single operand register.
Claim 6
Dependent Claim
27 words
The apparatus of claim 4, wherein the subtracter circuit further comprises a divide-by-two circuit having means for right-shifting the trailing zero detection circuit output one bit position.
Claim 7
Dependent Claim
28 words
The apparatus of claim 5, further comprising a root fraction register having means for storing the square root value of the operand value stored in the operand register.
Claim 8
Dependent Claim
35 words
The apparatus of claim 6, further comprising a trailing zero detector circuit connected to said root fraction register, including means for providing an output comprising the number of trailing zeroes in said root fraction register.
Claim 9
Dependent Claim
56 words
The apparatus of claim 7, wherein said comparator further comprises an input connection to receive the number of trailing zeroes in said root fraction register, and further comprises means for generating a first output signal when said number of trailing zeroes in said root fraction register is equal to the right-shifted output from the divide-by-two circuit.
Claim 10
Dependent Claim
38 words
The apparatus of claim 8, wherein said comparator further comprises means for generating a second output signal when said number of trailing zeroes in said root fraction register is unequal to the right-shifted output from the divide-by-two circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |