Decoupling capacitor, wafer stack package including the decoupling capacitor, and method of fabricating the wafer stack package

Claim 2

A decoupling capacitor, comprising: a first electrode formed on an upper surface of a first wafer; a second electrode formed on a lower surface of a second wafer; and an adhesive material having a high dielectric constant, the adhesive material adhering the first wafer and the second wafer together, wherein the first and second electrodes operate as two electrodes of the decoupling capacitor, and the adhesive material operates as a dielectric of the decoupling capacitor, and wherein conductive perpendicular vias are formed in the first and second wafers to connect semiconductor devices formed on the first and second wafers to signals, power sources, and grounds, and wherein the first electrode is connected to power vias configured to connect the semiconductor devices to the power sources, and the second electrode is connected to ground vias configured to connect the semiconductor devices to the grounds.

Claim 3

The decoupling capacitor of claim 1 , wherein the first electrode is a conductive thin plane formed on the upper surface of the first wafer, and the second electrode is a conductive thin plane formed on the lower surface of the second wafer.

Claim 4

The decoupling capacitor of claim 2 , wherein the conductive thin planes have forms suitable to maximize a capacitance of the decoupling capacitor.

Claim 5

The decoupling capacitor of claim 2 , wherein the conductive thin planes are respectively formed on substantially the entire upper and lower surfaces of the first and second wafers except for connection parts for electrical connections to semiconductor devices formed on the first and second wafers.

Claim 6

The decoupling capacitor of claim 1 , wherein the first and second electrodes are respectively formed on substantially the entire upper and lower surfaces of the first and second wafers except for parts in which the vias for connecting the semiconductor devices are formed, and wherein if the semiconductor devices formed on the first wafer use at least two different powers, the power vias are divided into sub-power vias connected to the at least two different power sources, the first electrode being electrically divided into sub-electrode areas corresponding to the semiconductor devices, where the divided sub-electrode areas of the first electrode are respectively connected to corresponding sub-power vias.

Claim 7

The decoupling capacitor of claim 1 , wherein the perpendicular vias in the first and second wafers are connected to each other through conductive bumps.

Claim 8

The decoupling capacitor of claim 1 , wherein a second electrode is formed on a lower surface of the first wafer, a first electrode is formed on an upper surface of the second wafer, and at least one other wafer is stacked on one of the first and second wafers to form at least two decoupling capacitors.

Claim 9

The decoupling capacitor of claim 7 , wherein first and second electrodes are respectively formed on upper and lower surfaces of the at least one other wafer, and the at least one other wafer is stacked on one of the first and second wafers using the adhesive material.

Claim 10

The decoupling capacitor of claim 8 , wherein a semiconductor device is formed on the at least one other wafer, wherein perpendicular vias are formed in the at least one other wafer to connect the semiconductor devices formed on the wafers to signals, the power sources, and the grounds are formed in the first, second, and at least one other wafer, and wherein first electrodes of the first, second, and at least one other wafer are connected to power vias to connect the semiconductor devices to the power sources, and second electrodes of the first, second, and at least one other wafer are connected to ground vias to connect the semiconductor devices to the grounds.

Claim 11

The decoupling capacitor of claim 1 , wherein the adhesive material has one of a single structure comprising BaTiO 3 or SrTiO 3 , and a multilayer structure in which adhesives are adhered on and underneath a high dielectric.

Claim 12

A wafer stack package comprising a decoupling capacitor, comprising: a printed circuit board (PCB); at least two wafers stacked on the PCB, wherein first electrodes are formed on first surfaces of the at least two wafers, and second electrodes are formed on second surfaces of the at least two wafers; and an adhesive material having a high dielectric constant, the adhesive material adhering the at least two wafers together, wherein one of the first and one of the second electrodes operate as electrodes of the decoupling capacitor, and the adhesive material operates as a dielectric of the decoupling capacitor to form the decoupling capacitor between the at least two wafers.

Claim 13

A wafer stack package comprising a decoupling capacitor, comprising: a printed circuit board (PCB); at least two wafers stacked on the PCB, wherein first electrodes are formed on first surfaces of the at least two wafers, and second electrodes are formed on second surfaces of the at least two wafers; and an adhesive material having a high dielectric constant, the adhesive material adhering the at least two wafers together, wherein one of the first and one of the second electrodes operate as electrodes of the decoupling capacitor, and the adhesive material operates as a dielectric of the decoupling capacitor to form the decoupling capacitor between the at least two wafers.

Claim 14

The wafer stack package of claim 11 , wherein the first electrodes are conductive thin planes formed on the first surfaces of the at least two wafers, and the second electrodes are conductive thin planes formed on the second surfaces of the at least two second surfaces.

Claim 15

The wafer stack package of claim 11 , wherein conductive perpendicular vias are formed in the at least two wafers to connect semiconductor devices formed on the at least two wafers to signals, power sources, and grounds, wherein the first electrodes are connected to power vias configured to connect the semiconductor devices to the power sources, and the second electrodes are connected to ground vias configured to connect the semiconductor devices to the grounds.

Claim 16

The wafer stack package of claim 13 , wherein the first and second electrodes are respectively formed substantially over the entire surfaces of the at least two wafers except for parts in which the vias are formed, and wherein if semiconductor devices formed on at least one of the at least two wafers use at least two different power sources, the power vias are divided into sub-power vias connected to the at least two different power sources, the first electrodes formed on the at least one wafer being electrically divided into sub-electrode areas of the semiconductor devices, where the divided parts of the first electrodes are respectively connected to the corresponding sub-power vias.

Claim 17

The wafer stack package of claim 13 , wherein the perpendicular vias are formed in outer end parts of the at least two wafers in which the semiconductor devices are formed.

Claim 18

The wafer stack package of claim 11 , wherein the first electrodes are connected to power sources of semiconductor devices formed on the at least two wafers through die cut lines formed on the at least two wafers, and the second electrodes are connected to grounds of the semiconductor devices formed on the at least two wafers through the die cut lines on the at least two wafers.

Claim 19

The wafer stack package of claim 11 , wherein the at least two wafers are electrically connected to an upper surface of the PCB using one of flip-chip bonding and wire bonding methods.

Claim 20

The wafer stack package of claim 17 , wherein solder balls are formed on a bottom surface of the PCB, and the at least two wafers stacked on the PCB are sealed using a sealant.

Claim 21

A semiconductor device, comprising: a first wafer having a first surface; a second wafer having a second surface, wherein the second wafer is disposed over the first wafer such that the first surface of the first wafer faces the second surface of the second wafer; a first electrode formed on the first surface of the first wafer; a second electrode formed on the second surface of the second wafer; and an adhesive material formed between the first and second electrode to adhere the first and second wafers together, wherein the first electrode, second electrode, and adhesive material are configured to operate as a decoupling capacitor, wherein the first wafer includes first semiconductor components and the second wafer includes second semiconductor components, and wherein each of the first and second wafers includes a plurality of vias respectively perpendicular to the first and second surfaces, the plurality of vias configured to connect the first and second semiconductor components to a power source, a ground, and communication signals.

Claim 22

A semiconductor device, comprising: a first wafer having a first surface; a second wafer having a second surface, wherein the second wafer is disposed over the first wafer such that the first surface of the first wafer faces the second surface of the second wafer; a first electrode formed on the first surface of the first wafer; a second electrode formed on the second surface of the second wafer; and an adhesive material formed between the first and second electrode to adhere the first and second wafers together, wherein the first electrode, second electrode, and adhesive material are configured to operate as a decoupling capacitor, wherein the first wafer includes first semiconductor components and the second wafer includes second semiconductor components, and wherein each of the first and second wafers includes a plurality of vias respectively perpendicular to the first and second surfaces, the plurality of vias configured to connect the first and second semiconductor components to a power source, a ground, and communication signals.

Claim 23

The semiconductor device of claim 19 , wherein the adhesive material comprises a high dielectric adhesive material.