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US7786573B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Packaging chip having interconnection electrodes directly connected to plural wafers

Assignee: Samsung Electronics Co Ltd
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Filing: 2006-07-06
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Granted: 2010-08-31
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Expires: 2026-07-06
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Abstract

Abstract A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

Inventors

  • 👤 Min-seog Choi
  • 👤 Kae-dong Back
  • 👤 In-Sang Song
  • 👤 Woon-bae Kim
  • 👤 Byung-Gil Jeong
  • 👤 Kyu-dong Jung

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 11:01
CPC Classifications
H; H10; H10W; H10W90/00; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0234; H10W20/20; H03; H03H; H03H9/00; H03H9/02; H03H9/05; H03H9/0538; H03H9/0547; H10W90/20; H10W90/297; H10W90/701; H10W90/721; H10W90/722; H10W99/00

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 94 words
A packaging chip, comprising: plural wafers which are stacked; and plural first and second interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers; wherein each interconnection electrode extends directly from the upper surface of the uppermost wafer to the upper surfaces of the different wafers, respectively, and a first plurality of interconnection electrodes do not penetrate through the wafer to which they are connected, and a second plurality of interconnection electrodes penetrate through the wafer to which they are connected.
Claim 2
Dependent Claim 94 words
A packaging chip, comprising: plural wafers which are stacked; and plural first and second interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers; wherein each interconnection electrode extends directly from the upper surface of the uppermost wafer to the upper surfaces of the different wafers, respectively, and a first plurality of interconnection electrodes do not penetrate through the wafer to which they are connected, and a second plurality of interconnection electrodes penetrate through the wafer to which they are connected.
Claim 3
Dependent Claim 27 words
The packaging chip as claimed in claim 1 , wherein at least one or more wafers of the plural wafers have a cavity of a predetermined size.
Claim 4
Dependent Claim 26 words
The packaging chip as claimed in claim 1 , wherein at least one or more of the plural wafers has a predetermined circuit device mounted thereon.
Claim 5
Dependent Claim 40 words
The packaging chip as claimed in claim 1 , further comprising plural pads independently arranged on the upper surface of the uppermost wafer, each of the plural pads is electrically connected to at least one of the plural interconnection electrodes.
Claim 6
Dependent Claim 19 words
The packaging chip as claimed in claim 1 , wherein the plural wafers are stacked in a predetermined order.
Claim 7
Dependent Claim 46 words
The packaging chip as claimed in claim 1 , wherein the wafers each have a different diameter, and wherein the wafers are arranged in a coaxial line in order of diameter size, such that a predetermined area of each of the plural wafers is externally exposed.

References Cited (Backward Citations)

US4954875A Cited
US5748452A Cited
US6297548B1 Cited
KR20010073345A Cited
KR20030046791A Cited
US6888253B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2013-08-30 2014-03-01 2014-08-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2017-08-30 2018-03-01 2018-08-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2021-08-30 2022-03-01 2022-08-31 $7700.00 Window Closed / Lapsed

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