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US7510934B2
Active / In Force
US
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Methods of fabricating nonvolatile memory devices
Assignee: Samsung Electronics Co Ltd
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Filing: 2007-05-29
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Granted: 2009-03-31
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Expires: 2027-05-29
Abstract
Abstract A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.
Inventors
- 👤 Seung-pil Chung
- 👤 Jong-Ho Park
- 👤 Kyeong-koo Chi
- 👤 Dong-Hyun Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:37
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30; H10B41/40; H10B41/42
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
212 words
A method of fabricating a nonvolatile memory device, the method comprising: forming trenches in a semiconductor substrate that define active regions therebetween; forming a device isolation film that fills the trenches in the substrate; forming a tunnel insulating film on the active regions of the substrate; forming a plurality of floating gates each on the tunnel insulating film over the active regions of the substrate; removing a portion of the device isolation film over the trenches in the substrate to expose sidewalls of the floating gates; recessing a region of the device isolation film in the trenches so that the recessed region has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches and so that an edge of the recessed region is aligned with a sidewall of an adjacent gate, wherein the floating gate is formed wider than the active region of the substrate and an edge portion of the floating gate partially overlaps a portion of the device isolation film in the trench; forming an inter-gate dielectric film extending across the floating gates and the device isolation film; and forming a control gate conductive film on the inter-gate dielectric film and extending across the floating gates.
Claim 2
Independent Claim
212 words
A method of fabricating a nonvolatile memory device, the method comprising: forming trenches in a semiconductor substrate that define active regions therebetween; forming a device isolation film that fills the trenches in the substrate; forming a tunnel insulating film on the active regions of the substrate; forming a plurality of floating gates each on the tunnel insulating film over the active regions of the substrate; removing a portion of the device isolation film over the trenches in the substrate to expose sidewalls of the floating gates; recessing a region of the device isolation film in the trenches so that the recessed region has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches and so that an edge of the recessed region is aligned with a sidewall of an adjacent gate, wherein the floating gate is formed wider than the active region of the substrate and an edge portion of the floating gate partially overlaps a portion of the device isolation film in the trench; forming an inter-gate dielectric film extending across the floating gates and the device isolation film; and forming a control gate conductive film on the inter-gate dielectric film and extending across the floating gates.
Claim 3
Dependent Claim
52 words
The method of claim 1 , wherein recessing a region of the device isolation film in the trenches comprises recessing the region of the device isolation film so that opposite edges of the recessed region of the device isolation film are aligned with facing sidewalls of adjacent ones of the floating gates.
Claim 4
Dependent Claim
33 words
The method of claim 1 , wherein the upper major surface of the recessed region of the device isolation film is below an upper major surface of the active region of the substrate.
Claim 5
Dependent Claim
26 words
The method of claim 1 , wherein opposite edge portions of a lower surface of the floating gates are formed directly on the device isolation film.
Claim 6
Dependent Claim
27 words
The method of claim 1 , wherein the inter-gate dielectric film is formed directly on at least one entire side surface of each of the floating gates.
Claim 7
Dependent Claim
28 words
The method of claim 1 , wherein the inter-gate dielectric film is formed directly on at least two opposite entire side surfaces of each of the floating gates.
Claim 8
Independent Claim
141 words
A method of fabricating a nonvolatile memory device, the method comprising: forming trenches in a semiconductor substrate that define active regions therebetween; forming a device isolation film that fills the trenches in the substrate; forming a tunnel insulating film on the active regions of the substrate; forming a plurality of floating gates each on the tunnel insulating film over the active regions of the substrate; isotropically etching a portion of the device isolation film between the floating gates to partially expose sidewalls of the floating gates; anisotropically etching another portion of the device isolation film between the floating gates to completely expose the sidewalls of the floating gates; forming an inter-gate dielectric film extending across the floating gates and the device isolation film; and forming a control gate conductive film on the inter-gate dielectric film and extending across the floating gates.
Claim 9
Independent Claim
141 words
A method of fabricating a nonvolatile memory device, the method comprising: forming trenches in a semiconductor substrate that define active regions therebetween; forming a device isolation film that fills the trenches in the substrate; forming a tunnel insulating film on the active regions of the substrate; forming a plurality of floating gates each on the tunnel insulating film over the active regions of the substrate; isotropically etching a portion of the device isolation film between the floating gates to partially expose sidewalls of the floating gates; anisotropically etching another portion of the device isolation film between the floating gates to completely expose the sidewalls of the floating gates; forming an inter-gate dielectric film extending across the floating gates and the device isolation film; and forming a control gate conductive film on the inter-gate dielectric film and extending across the floating gates.
Claim 10
Dependent Claim
110 words
The method as of claim 7 , wherein: forming trenches in a semiconductor substrate comprises: forming a hard mask pattern on the semiconductor substrate; and etching the substrate with the hard mask pattern as an etch mask to form the trenches; forming a tunnel insulating film comprises: removing the hard mask pattern to expose the active regions of the substrate; and forming the tunnel insulation film on the substrate exposed by removing the hard mask pattern; and forming a plurality of floating gates comprises: forming a conductive film on the device isolation film and the tunnel insulating film; and polishing the conductive film until the device isolation film is exposed.
Claim 11
Dependent Claim
52 words
The method of claim 8 , wherein forming a plurality of floating gates further comprises removing a portion of the device isolation film to form an opening that extends across the active regions of the substrate and overlaps a portion of the trenches, and the conductive film is formed in the opening.
Claim 12
Dependent Claim
50 words
The method of claim 8 , wherein forming a plurality of floating gates comprises forming each of the floating gates wider than an adjacent active region of the substrate and so that edge portions of each floating gate extend over a portion of the device isolation film in the trenches.
Claim 13
Dependent Claim
45 words
The method of claim 8 , wherein isotropically etching a portion of the device isolation film between the floating gates to partially expose sidewalls of the floating gates comprises stopping the isotropic etching of the device isolation film before the tunnel insulation film is exposed.
Claim 14
Dependent Claim
43 words
The method of claim 8 , wherein anisotropically etching another portion of the device isolation film between the floating gates to completely expose the sidewalls of the floating gates comprises etching the device isolation film with the floating gates as an etch mask.
Claim 15
Dependent Claim
87 words
The method of claim 12 , wherein etching the device isolation film with the floating gates as an etch mask comprises recessing a region of the device isolation film in the trenches so that the recessed region has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches and an edge of the recessed region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.
Claim 16
Dependent Claim
29 words
The method of claim 13 , wherein the upper major surface of the recessed region of the device isolation film is below a lower surface of the floating gates.
Claim 17
Dependent Claim
37 words
The method of claim 13 , wherein the inter-gate dielectric film is formed on the device isolation film including the recessed region and is separated from the active regions of the substrate by the device isolation film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2012-03-30 | 2012-09-29 | 2013-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2016-03-30 | 2016-09-29 | 2017-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2020-03-30 | 2020-09-29 | 2021-03-31 | $7700.00 | Window Closed / Lapsed |