Patent US7489171B2 successfully refreshed from Google Patents.
US7489171B2
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US
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Adaptive delay-locked loops and methods of generating clock signals using the same
Assignee: Samsung Electronics Co Ltd
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Filing: 2007-02-21
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Granted: 2009-02-10
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Expires: 2027-02-21
Abstract
Abstract A delay-locked loop (DLL) includes a delay line and a control circuit. The delay line delays an input clock signal based on at least one phase control signal to generate an output clock signal. The at least one phase control signal indicates whether the output clock signal leads or lags the input clock signal. The control circuit generates a division control signal by determining whether the output clock signal is locked with respect to the input clock signal, and generates the at least one phase control signal based on the division control signal. Accordingly, a locking time and bang-bang jitter may be reduced.
Inventors
- 👤 In-Dal Song
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:48
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/081; H03L7/0812; H03L7/0814; H03L7/10; H03L7/107; H03L7/095
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
93 words
A delay-locked loop (DLL) comprising: a delay line configured to delay an input clock signal based on at least one phase control signal to generate an output clock signal, the at least one phase control signal indicating whether the output clock signal leads or lags the input clock signal; and a control circuit configured to generate a division control signal by determining whether the output clock signal is locked with respect to the input clock signal, and configured to generate the at least one phase control signal based on the division control signal.
Claim 2
Dependent Claim
93 words
A delay-locked loop (DLL) comprising: a delay line configured to delay an input clock signal based on at least one phase control signal to generate an output clock signal, the at least one phase control signal indicating whether the output clock signal leads or lags the input clock signal; and a control circuit configured to generate a division control signal by determining whether the output clock signal is locked with respect to the input clock signal, and configured to generate the at least one phase control signal based on the division control signal.
Claim 3
Dependent Claim
53 words
The DLL of claim 1 , further comprising, a local clock generator configured to generate a local clock signal by controlling a frequency of the local clock signal based on the division control signal, wherein the control circuit generates the at least one phase control signal in synchronization with the local clock signal.
Claim 4
Dependent Claim
33 words
The DLL of claim 2 , wherein the control circuit includes, a logic circuit configured to determine whether the output clock signal is locked based on the at least one phase control signal.
Claim 5
Dependent Claim
68 words
The DLL of claim 3 , wherein the logic circuit determines the output clock signal is in a locked state when a first of the at least one phase control signal is continuously generated more than N number of times and then another of the at least one phase control signal is generated subsequent to the continuous generation of the first phase control signal N number of times.
Claim 6
Dependent Claim
53 words
The DLL of claim 3 , wherein the logic circuit determines the output clock signal is in an unlocked state when a first of the at least one phase control signal is continuously generated more than N number of times after the output clock signal is determined to be in a locked state.
Claim 7
Dependent Claim
57 words
The DLL of claim 2 , wherein the control circuit generates the division control signal having a first logic value when the output clock signal is determined to be in a locked state, and generates the division control signal having a second logic value when the output clock signal is determined to be in an unlocked state.
Claim 8
Dependent Claim
59 words
The DLL of claim 6 , wherein the local clock generator generates the local clock signal with a first frequency while the division control signal has the first logic value, and generates the local clock signal with a second frequency while the division control signal has the second logic value, the first frequency being lower than the second frequency.
Claim 9
Dependent Claim
72 words
The DLL of claim 6 , wherein the local clock generator generates the local clock signal with a frequency lower than a loop bandwidth of the DLL while the division control signal has the first logic value, and generates the local clock signal with a frequency between the loop bandwidth of the DLL and a maximum operating frequency of the control circuit while the division control signal has the second logic value.
Claim 10
Dependent Claim
35 words
The DLL of claim 1 , wherein the delay line is further configured to update a phase of the output clock signal with a respective phase variation according to an operating mode of the DLL.
Claim 11
Dependent Claim
84 words
The DLL of claim 1 , wherein the delay line includes, a coarse delay line configured to generate a plurality of coarse delay signals having a first phase variation, a selector configured to select at least two of the plurality of coarse delay signals to output the selected coarse delay signals, and an interpolator configured to generate the output clock signal having a second phase variation by interpolating the selected coarse delay signals, the second phase variation being less than the first phase variation.
Claim 12
Dependent Claim
64 words
The DLL of claim 1 , wherein the delay line includes, a coarse delay line configured to generate one coarse delay signal having a first phase variation, and a phase blender configured to generate the output clock signal by select one of the coarse delay signal and a plurality of second delay signals delayed for a respective delay time from the coarse delay signal.
Claim 13
Dependent Claim
32 words
The DLL of claim 1 , wherein the control circuit is further configured to control a generation frequency of the at least one phase control signal based on the division control signal.
Claim 14
Dependent Claim
74 words
The DLL of claim 12 , wherein the control circuit generates the at least one phase control signal with a first frequency when the division control signal indicates the output clock signal is in a locked state, and generates the at least one phase control signal with a second frequency when the division control signal indicates the output clock signal is in an unlocked state, the first frequency being lower than the second frequency.
Claim 15
Dependent Claim
58 words
The DLL of claim 12 , wherein the control circuit includes, a logic circuit configured to determine a phase difference between the input clock signal and the output clock signal based on a first phase control signal and a second phase control signal, the at least one phase control signal including the first and second phase control signals.
Claim 16
Dependent Claim
51 words
The DLL of claim 14 , wherein the logic circuit determines whether the output clock signal is in a locked state or an unlocked state with respect to the input clock signal based on a generation sequence of the first and second phase control signals to generate the division control signal.
Claim 17
Dependent Claim
78 words
The DLL of claim 15 , wherein the logic circuit determines the output clock signal is in a locked state when one of the first and second phase control signals is continuously generated more than N number of times and then another of the first and second phase control signals is generated, the logic circuit outputting the division control signal having a first logic value if the output clock signal is determined to be in a locked state.
Claim 18
Dependent Claim
82 words
The DLL of claim 15 , wherein the logic circuit determines that the output clock signal is in an unlocked state when one of the first and second phase control signals is continuously generated more than a N number of times after the output clock signal is determined to be in a locked state, the logic circuit outputting the division control signal having a second logic value if the if the output clock signal is determined to be in an unlocked state.
Claim 19
Dependent Claim
69 words
The DLL of claim 17 , wherein the logic circuit is configured to perform a logical NAND operation on a number of the first phase control signals to obtain a first result, perform a logical NAND operation on a number of the second phase control signals to obtain a second result, and perform a logical NAND operation on the first and second results to generate the division control signal.
Claim 20
Dependent Claim
96 words
The DLL of claim 14 , wherein the control circuit is configured to generates the first and second phase control signals with a frequency between a loop bandwidth of the DLL and a maximum operating frequency of the control circuit when the division control signal indicates the output clock signal is in a locked state, and the control circuit is configured to generate the first and second phase control signals with a frequency lower than the loop bandwidth of the DLL when the division control signal indicates the output clock signal is in an unlocked state.
Claim 21
Independent Claim
86 words
A method of generating an output clock signal, the method comprising: delaying an input clock signal based on at least one phase control signal to generate an output clock signal, the at least one phase control signal indicating whether the output clock signal leads or lags the input clock signal; generating a division control signal by determining whether the output clock signal is locked with respect to the input clock signal; and generating the at least one phase control signal based on the division control signal.
Claim 22
Independent Claim
86 words
A method of generating an output clock signal, the method comprising: delaying an input clock signal based on at least one phase control signal to generate an output clock signal, the at least one phase control signal indicating whether the output clock signal leads or lags the input clock signal; generating a division control signal by determining whether the output clock signal is locked with respect to the input clock signal; and generating the at least one phase control signal based on the division control signal.
Claim 23
Dependent Claim
45 words
The method of claim 20 , further including, generating a local clock signal by controlling a frequency of the local clock signal based on the division control signal, wherein the at least one phase control signal is generated in synchronization with the local clock signal.
Claim 24
Dependent Claim
53 words
The method of claim 21 , wherein the output clock signal is determined to be in a locked state when a first of the at least one phase control signal is continuously generated more than N number of times and then a second of the at least one phase control signal is generated.
Claim 25
Dependent Claim
52 words
The method of claim 21 , wherein the output clock signal is determined to be in an unlocked state when a first of the at least one phase control signal is continuously generated more than N number of times after the output clock signal is determined to be in a locked state.
Claim 26
Dependent Claim
60 words
The method of claim 21 , wherein generating the division control signal includes, generating the division control signal having a first logic value when the output clock signal is determined to be in a locked state, and generating the division control signal having a second logic value when the output clock signal is determined to be in an unlocked state.
Claim 27
Dependent Claim
61 words
The method of claim 24 , wherein generating the local clock signal includes, generating the local clock signal with a first frequency while the division control signal has the first logic value, and generating the local clock signal with a second frequency while the division control signal has the second logic value, the first frequency being lower than the second frequency.
Claim 28
Dependent Claim
66 words
The method of claim 24 , wherein generating the local clock signal includes, generating the local clock signal with a frequency lower than a loop bandwidth of the DLL while the division control signal has the first logic value, and generating the local clock signal with a frequency higher than the loop bandwidth of the DLL while the division control signal has the second logic value.
Claim 29
Dependent Claim
112 words
The method of claim 20 , further including, detecting a phase difference between the input clock signal and the output clock signal to generate the division control signal based on the phase difference, updating a phase of the output clock signal with a first phase-update frequency and a first phase variation during a fine locking time interval when the division control signal indicates the output clock signal is in a locked state, and updating the phase of the output clock signal with a second phase-update frequency and a second phase variation during the fine locking time interval when the division control signal indicates the output clock signal is in an unlocked state.
Claim 30
Dependent Claim
18 words
The method of claim 27 , wherein the first phase-update frequency is lower than the second phase-update frequency.
Claim 31
Dependent Claim
45 words
The method of claim 27 , further including, updating the phase of the output clock signal with a third phase-update frequency and a third phase variation during a coarse locking time interval, the third phase variation being greater than the first and second phase variation.
Claim 32
Dependent Claim
77 words
The method of claim 27 , further including, updating the phase of the output clock signal with a phase-update frequency higher than a loop bandwidth of a DLL and a phase variation greater than the first and second phase variations until the output clock signal is determined to be in a locked state, if the phase of the output clock signal is determined to be out of a first phase difference during the fine locking time interval.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2012-02-10 | 2012-08-11 | 2013-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2016-02-10 | 2016-08-11 | 2017-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2020-02-10 | 2020-08-11 | 2021-02-10 | $7700.00 | Window Closed / Lapsed |