US7391667B2
Expired / Lapsed
US
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Semiconductor integrated circuit
Assignee: NEC Electronics Corp
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Filing: 2006-10-18
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Granted: 2008-06-24
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Expires: 2026-10-18
Abstract
Abstract An apparatus is to reduce, during the standby time, the electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.
Inventors
- 👤 Bryan Atwood
- 👤 Takao Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:21
CPC Classifications
G; G11; G11C; G11C7/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; H; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
110 words
A semiconductor integrated circuit comprising: a memory cell including a storage transistor for storing an electric charge in a gate capacitance; a write bit line coupled to a gate electrode of the storage transistor; a read bit line coupled to a drain electrode of the storage transistor; and a switching element provided between a source electrode of the storage transistor and a power supply; wherein the switching element controls a potential of the source electrode of the storage transistor so that in a standby state the source electrode stays in a floating state, and in a read operation state the potential of the source electrode becomes a power supply potential.
Claim 2
Dependent Claim
110 words
A semiconductor integrated circuit comprising: a memory cell including a storage transistor for storing an electric charge in a gate capacitance; a write bit line coupled to a gate electrode of the storage transistor; a read bit line coupled to a drain electrode of the storage transistor; and a switching element provided between a source electrode of the storage transistor and a power supply; wherein the switching element controls a potential of the source electrode of the storage transistor so that in a standby state the source electrode stays in a floating state, and in a read operation state the potential of the source electrode becomes a power supply potential.
Claim 3
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 1 , further comprising: an access transistor for controlling conduction between the read bit line and the drain electrode of the storage transistor.
Claim 4
Dependent Claim
32 words
A semiconductor integrated circuit according to claim 1 , further comprising: a write transistor for supplying the electric charge from the write bit line to the gate electrode of the storage transistor.
Claim 5
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 3 , wherein a channel area of the write transistor is formed of a film having a film thickness of 5 nm or less.
Claim 6
Dependent Claim
37 words
A semiconductor integrated circuit according to claim 4 , wherein a source/drain path of the write transistor is formed in a direction perpendicular to a direction in which a source/drain path of the storage transistor is formed.
Claim 7
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 1 , further comprising: a second memory cell provided with the switching element in common.
Claim 8
Dependent Claim
106 words
A semiconductor integrated circuit comprising: a memory cell including a storage transistor for storing an electric charge in a gate capacitance; a write bit line coupled to a gate electrode of the storage transistor; a read bit line coupled to a drain electrode of the storage transistor; and a switching element provided between the read bit line and a power supply; wherein the switching element controls a potential of the read bit line so that in a standby state the read bit line stays in a floating state, and in a read operation state the potential of the read bit line becomes a power supply potential.
Claim 9
Dependent Claim
106 words
A semiconductor integrated circuit comprising: a memory cell including a storage transistor for storing an electric charge in a gate capacitance; a write bit line coupled to a gate electrode of the storage transistor; a read bit line coupled to a drain electrode of the storage transistor; and a switching element provided between the read bit line and a power supply; wherein the switching element controls a potential of the read bit line so that in a standby state the read bit line stays in a floating state, and in a read operation state the potential of the read bit line becomes a power supply potential.
Claim 10
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 7 , further comprising: an access transistor for controlling conduction between the read bit line and the drain electrode of the storage transistor.
Claim 11
Dependent Claim
32 words
A semiconductor integrated circuit according to claim 7 , further comprising: a write transistor for supplying the electric charge from the write bit line to the gate electrode of the storage transistor.
Claim 12
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 9 , wherein a channel area of the write transistor is formed of a film having a film thickness of 5 nm or less.
Claim 13
Dependent Claim
37 words
A semiconductor integrated circuit according to claim 9 , wherein a source/drain path of the write transistor is formed in a direction perpendicular to a direction in which a source/drain path of the storage transistor is formed.
Claim 14
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 7 , further comprising: a second memory cell provided with the switching element in common.
Claim 15
Dependent Claim
94 words
A semiconductor integrated circuit comprising: a memory cell including a storage transistor for storing an electric charge in a gate capacitance; a write bit line coupled to a gate electrode of the storage transistor; a read bit line coupled to a drain electrode of the storage transistor; and a switching element provided between a source electrode of the storage transistor and a power supply potential; wherein in a standby state, a potential of the source of the storage transistor and a potential of the read bit line are controlled to become an equal potential.
Claim 16
Dependent Claim
94 words
A semiconductor integrated circuit comprising: a memory cell including a storage transistor for storing an electric charge in a gate capacitance; a write bit line coupled to a gate electrode of the storage transistor; a read bit line coupled to a drain electrode of the storage transistor; and a switching element provided between a source electrode of the storage transistor and a power supply potential; wherein in a standby state, a potential of the source of the storage transistor and a potential of the read bit line are controlled to become an equal potential.
Claim 17
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 13 , further comprising: an access transistor for controlling conduction between the read bit line and the drain electrode of the storage transistor.
Claim 18
Dependent Claim
32 words
A semiconductor integrated circuit according to claim 13 , further comprising: a write transistor for supplying the electric charge from the write bit line to the gate electrode of the storage transistor.
Claim 19
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 15 , wherein a channel area of the write transistor is formed of a film having a film thickness of 5 nm or less.
Claim 20
Dependent Claim
37 words
A semiconductor integrated circuit according to claim 16 , wherein a source/drain path of the write transistor is formed in a direction perpendicular to a direction in which a source/drain path of the storage transistor is formed.
Claim 21
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 13 , further comprising: a second memory cell provided with the switching element in common.
References Cited (Backward Citations)
US5831896A
Cited
US5995433A
Cited
JP2000011642A
Cited
US6576943B1
Cited
US6452834B1
Cited
US6787835B2
Cited
US6809979B1
Cited
US6903962B2
Cited
US7139214B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2011-06-24 | 2011-12-24 | 2012-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2015-06-24 | 2015-12-24 | 2016-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2019-06-24 | 2019-12-24 | 2020-06-24 | $7700.00 | Window Closed / Lapsed |