Semiconductor device for reducing leak currents and controlling a threshold voltage and using a thin channel structure

Claim 2

A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region, and a control electrode for controlling conductance of said semiconductor region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; and a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; and wherein a channel of said write transistor structure is made of a semiconductor film 5 nm at most in average thickness.

Claim 3

A semiconductor memory element according to claim 1 , wherein said channel of said write transistor structure is constituted by polycrystal silicon.

Claim 4

A semiconductor memory element according to claim 1 , wherein a distance between a channel of said write transistor structure and said charge accumulating region is 10 nm at most.

Claim 5

A semiconductor memory element according to claim 1 , wherein a distance between a channel of said write transistor structure and said charge accumulating region is 7 nm at most.

Claim 6

A semiconductor memory element according to claim 1 , wherein a gate insulating film of said write transistor structure is 15 nm thick at most.

Claim 7

A semiconductor memory element according to claim 1 , wherein a gate insulating film of said write transistor structure is 10 nm thick at most.

Claim 8

A semiconductor memory element according to claim 1 , wherein said source region and said drain region of said write transistor are constituted by polycrystal silicon.

Claim 9

A semiconductor memory element according to claim 1 , wherein a channel of said write transistor structure is provided so as to cause currents moving through the structure to flow in substantially perpendicular relation to a substrate.

Claim 10

A semiconductor memory element according to claim 8 , wherein said channel of said write transistor structure has a shape similar to a side surface of any one of a cylinder, a square pole and an intermediate form therebetween, wherein said any one of said cylinder, said square pole and said intermediate form is furnished in a substantially vertical direction.

Claim 11

A semiconductor memory element according to claim 8 , wherein said channel of said write transistor structure is located on an inner side of a hole provided in a substantially vertical direction.

Claim 12

A semiconductor memory element according to claim 10 , wherein at least part of a control electrode of said write transistor structure is located on an inner side of a region surrounded by said channel.

Claim 13

A semiconductor memory element according to claim 1 , wherein said control electrode of said read transistor structure doubles as a control electrode of said write transistor structure.

Claim 14

A semiconductor memory device comprising a plurality of semiconductor memory elements according to claim 12 , wherein said drain regions of said read transistor structures in said plurality of semiconductor memory elements are interconnected; wherein drain regions of said write transistor structures in said plurality of semiconductor memory elements are interconnected, and so are said control electrodes of said write transistor structures; wherein the connected drain regions of said read transistor structures are arranged in a substantially parallel relation with the connected drain regions of said write transistor structures; and wherein the connected drain regions of said read transistor structures are arranged in a substantially perpendicular relation to the connected control electrodes of said write transistors.

Claim 15

A semiconductor memory element according to claim 1 , wherein said control electrode of said read transistor structure and a drain region of said write transistor structure are provided in an integral fashion.

Claim 16

A semiconductor memory device comprising a plurality of semiconductor memory elements according to claim 14 , wherein said drain regions of said read transistor structures in said plurality of semiconductor memory elements are interconnected; wherein said drain regions of said write transistor structures in said plurality of semiconductor memory elements are interconnected, and so are control electrodes of said write transistor structures; wherein the connected drain regions of said read transistor structures are arranged in a substantially parallel relation with the connected control electrodes of said write transistor structures; and wherein the connected drain regions of said read transistor structures are arranged in a substantially perpendicular relation to the connected drain regions of said write transistors.

Claim 17

A semiconductor memory device comprising a plurality of semiconductor memory elements according to claim 1 , wherein, at least between two adjacent semiconductor memory elements, said source regions and said drain regions of said read transistor structures are interconnected.

Claim 18

A semiconductor memory device according to claim 16 , wherein said source regions and said drain regions of said read transistors are connected by an impurity diffusion layer.

Claim 19

A semiconductor memory element according to claim 1 , wherein said read transistor structure is connected via another transistor structure to a read data line.

Claim 20

A semiconductor memory device either comprising a plurality of semiconductor memory elements claimed in claim 1 ; wherein a difference between potentials fed to said semiconductor memory elements in said semiconductor memory device is 5 V at most.

Claim 21

A semiconductor memory device either comprising a plurality of semiconductor memory elements claimed in claim 1 ; wherein a potential fed to write word line connected to said write transistor structure is plus or minus 5 V at most and preferably plus or minus 3 V at most.

Claim 22

A semiconductor memory device either comprising a plurality of semiconductor memory elements claimed in claim 1 ; wherein said semiconductor memory device is refreshed only in one of two cases: when a data processor including the device is either turned on or turned off, or when said data processor is both turned on and turned off.

Claim 23

A semiconductor memory device either comprising a plurality of semiconductor memory elements claimed in claim 1 ; wherein, in a write operation to said semiconductor memory device, application of a write pulse is not followed by verification of written data.

Claim 24

A semiconductor memory element comprising: a substrate; a read transistor structure having a source region and a drain region formed in said substrate, and a channel region for interconnecting said source region and said drain region; a charge accumulating region located near said channel region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein at least part of a channel of said write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of said substrate; and wherein said semiconductor film is 5 nm at most in average thickness and deposited on a side of a convex formation on said principal plane of said substrate.

Claim 25

A semiconductor memory element comprising: a substrate; a read transistor structure having a source region and a drain region formed in said substrate, and a channel region for interconnecting said source region and said drain region; a charge accumulating region located near said channel region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein at least part of a channel of said write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of said substrate; and wherein said semiconductor film is 5 nm at most in average thickness and deposited on a side of a convex formation on said principal plane of said substrate.

Claim 26

A semiconductor memory element comprising: a substrate; a read transistor structure having a source region and a drain region formed in said substrate, and a channel region for interconnecting said source region and said drain region; a charge accumulating region located near said channel region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein at least part of a channel of said write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of said substrate; and wherein either a source region or a drain region of said write transistor structure is formed by a film deposited on said principal plane of said substrate.

Claim 27

A semiconductor memory element comprising: a substrate; a read transistor structure having a source region and a drain region formed in said substrate, and a channel region for interconnecting said source region and said drain region; a charge accumulating region located near said channel region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein at least part of a channel of said write transistor is formed by a semiconductor film deposited on a surface intersecting a principal plane of said substrate; and wherein either a source region or a drain region of said write transistor structure is formed by a film deposited on said principal plane of said substrate.

Claim 28

A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region, and a control electrode for controlling conductance of said semiconductor region between said source region and said drain region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; wherein a distance between a channel of said read transistor structure and said charge accumulating region is 10 nm at most and preferably 7 nm at most; and wherein a gate insulating film of said write transistor structure is 15 nm thick at most.

Claim 29

A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region, and a control electrode for controlling conductance of said semiconductor region between said source region and said drain region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; wherein a distance between a channel of said read transistor structure and said charge accumulating region is 10 nm at most and preferably 7 nm at most; and wherein a gate insulating film of said write transistor structure is 15 nm thick at most.

Claim 30

A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region, and a control electrode for controlling conductance of said semiconductor region between said source region and said drain region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; wherein a distance between a channel of said read transistor structure and said charge accumulating region is 10 nm at most and preferably 7 nm at most; and wherein said source region and said drain region of said write transistor are constituted by polycrystal silicon.

Claim 31

A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region, and a control electrode for controlling conductance of said semiconductor region between said source region and said drain region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; wherein a distance between a channel of said read transistor structure and said charge accumulating region is 10 nm at most and preferably 7 nm at most; and wherein said source region and said drain region of said write transistor are constituted by polycrystal silicon.

Claim 32

A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region, and a control electrode for controlling conductance of said semiconductor region between said source region and said drain region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; wherein a distance between a channel of said read transistor structure and said charge accumulating region is 10 nm at most and preferably 7 nm at most; and wherein a channel of said write transistor structure is provided so as to cause currents moving through the structure to flow in substantially perpendicular relation to a substrate.

Claim 33

A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region, and a control electrode for controlling conductance of said semiconductor region between said source region and said drain region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; wherein a distance between a channel of said read transistor structure and said charge accumulating region is 10 nm at most and preferably 7 nm at most; and wherein a channel of said write transistor structure is provided so as to cause currents moving through the structure to flow in substantially perpendicular relation to a substrate.

Claim 34

A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region, and a control electrode for controlling conductance of said semiconductor region between said source region and said drain region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; wherein a distance between a channel of said read transistor structure and said charge accumulating region is 10 nm at most and preferably 7 nm at most; and wherein a gate insulating film of said write transistor structure is 10 nm thick at most.

Claim 35

A semiconductor memory element comprising: a read transistor structure made of a source region, a drain region, a semiconductor region for interconnecting said source region and said drain region, and a control electrode for controlling conductance of said semiconductor region between said source region and said drain region; a charge accumulating region located near said semiconductor region for interconnecting said source region and said drain region; a write transistor structure for either electrically charging or electrically discharging said charge accumulating region; wherein an amount of electrical charges stored in said charge accumulating region changes conductance between said source region and said drain region in said read transistor structure, the conductance change being utilized for data storage; wherein a distance between a channel of said read transistor structure and said charge accumulating region is 10 nm at most and preferably 7 nm at most; and wherein a gate insulating film of said write transistor structure is 10 nm thick at most.