US6809979B1
Expired / Lapsed
US
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Complete refresh scheme for 3T dynamic random access memory cells
Assignee: Fernandez and Associates LLP
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Filing: 2003-03-04
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Granted: 2004-10-26
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Expires: 2023-03-04
Abstract
Abstract A refresh scheme for a semiconductor memory macro that comprises three-transistor dynamic random access memory (3T-DRAM) cells. Similar to an internal refresh operation, an external access command is also interpreted as a read-then-write operation. A clock cycle is partitioned as a plurality of time slots by an internal clock generator. Each time slot is assigned to execute a specific memory cell operations, whereby array idle time typically needed for performing exclusively non-array operations is no longer required. An external access and an internal refresh can be operated sequentially without degrading speed performance. An internal refresh can occur in every clock cycle period to retain the stored data. This clock cycle period is less than the time required for consecutively performing the external access and thereafter the internal refresh upon the completion of the external access.
Inventors
- 👤 Robin Tang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:40
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/403; G11C11/405
Claims Analysis
Total Claims: 70
Claim 1
Independent Claim
128 words
A method for refreshing three-transistor dynamic random access memory (3T-DRAM) cells of a 3T-DRAM sub-array, the method comprising the steps of: a) in a clock cycle, initiating an external access operation on a first cell; and b) in the clock cycle, before completing the external access operation on the first cell, initiating an internal refresh operation on a second cell of the sub-array, wherein the duration of the external access operation and the duration of the refresh operation overlaps to allow both the external access operation and the internal refresh operation to be completed effectively in one clock cycle period that is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 2
Independent Claim
128 words
A method for refreshing three-transistor dynamic random access memory (3T-DRAM) cells of a 3T-DRAM sub-array, the method comprising the steps of: a) in a clock cycle, initiating an external access operation on a first cell; and b) in the clock cycle, before completing the external access operation on the first cell, initiating an internal refresh operation on a second cell of the sub-array, wherein the duration of the external access operation and the duration of the refresh operation overlaps to allow both the external access operation and the internal refresh operation to be completed effectively in one clock cycle period that is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 3
Dependent Claim
27 words
The method of claim 1 , wherein the external access operation is adapted to be performed as an external read access followed by an external write access.
Claim 4
Dependent Claim
27 words
The method of claim 2 , wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access.
Claim 5
Dependent Claim
31 words
The method of claim 3 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 6
Dependent Claim
38 words
The method of claim 1 , wherein said step b) further comprising the step of: b1) inhibiting the internal refresh operation for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 7
Dependent Claim
38 words
The method of claim 1 , wherein said step c) further comprising the step of: c1) inhibiting the internal refresh operation for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 8
Independent Claim
104 words
A method for refreshing a three-transistor dynamic random access memory (3T-DRAM), the method comprising the steps of: a) in a clock cycle, while performing non-array operations, performing array operation of external access to a first cell of the 3T-DRAM sub-array to eliminate array idle time, wherein no portion of the clock cycle need to be devoted exclusively to non-array operations; and b) in the clock cycle, while performing non-array operations, performing array operation of internal refresh to a second cell of the 3T-DRAM sub-array to eliminate array idle time, wherein no portion of the clock cycle need to be devoted exclusively to non-array operations.
Claim 9
Independent Claim
104 words
A method for refreshing a three-transistor dynamic random access memory (3T-DRAM), the method comprising the steps of: a) in a clock cycle, while performing non-array operations, performing array operation of external access to a first cell of the 3T-DRAM sub-array to eliminate array idle time, wherein no portion of the clock cycle need to be devoted exclusively to non-array operations; and b) in the clock cycle, while performing non-array operations, performing array operation of internal refresh to a second cell of the 3T-DRAM sub-array to eliminate array idle time, wherein no portion of the clock cycle need to be devoted exclusively to non-array operations.
Claim 10
Dependent Claim
27 words
The method of claim 7 , wherein the external access operation is adapted to be performed as an external read access followed by an external write access.
Claim 11
Dependent Claim
27 words
The method of claim 8 , wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access.
Claim 12
Dependent Claim
31 words
The method of claim 9 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 13
Dependent Claim
38 words
The method of claim 7 , wherein said step b) further comprising the step of: b1) inhibiting the internal refresh operation for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 14
Dependent Claim
15 words
The method claim 7 , wherein the non-array operations comprise address decoding and data output.
Claim 15
Independent Claim
138 words
A method for accessing a three-transistor dynamic random access memory (3T-DRAM) sub-array, the method comprising the steps of: a) partitioning a clock cycle to begin with a first time segment and end with a second time segment, wherein the first time segment overlaps with the second time segment; b) assigning the first time segment of the clock cycle for performing an external access operation on a first cell of the 3T-DRAM sub-array; and c) assigning the second time segment of the clock cycle for performing an internal refresh operation on a second cell of the 3T-DRAM sub-array, wherein one internal refresh operation can be performed in every clock cycle period that is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 16
Independent Claim
138 words
A method for accessing a three-transistor dynamic random access memory (3T-DRAM) sub-array, the method comprising the steps of: a) partitioning a clock cycle to begin with a first time segment and end with a second time segment, wherein the first time segment overlaps with the second time segment; b) assigning the first time segment of the clock cycle for performing an external access operation on a first cell of the 3T-DRAM sub-array; and c) assigning the second time segment of the clock cycle for performing an internal refresh operation on a second cell of the 3T-DRAM sub-array, wherein one internal refresh operation can be performed in every clock cycle period that is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 17
Dependent Claim
24 words
The method of claim 13 , wherein the external access operation is performed as an external read access followed by an external write access.
Claim 18
Dependent Claim
26 words
The method of claim 13 , wherein the internal refresh operation is performed as an internal refresh read access followed by an internal refresh write access.
Claim 19
Dependent Claim
100 words
The method of claim 13 , said step a) further comprising the steps of: a1) partitioning the first time segment into a plurality of time slots that are used for a read access followed by a write access to the first 3T-DRAM cell; and a2) partitioning the second time segment into a second plurality of time slots that are used for a read access followed by a write access to the second 3T-DRAM cell, wherein the beginning time slot of the second plurality of time slots overlaps with the ending time slot of the first plurality of the time slots.
Claim 20
Dependent Claim
31 words
The method of claim 16 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 21
Dependent Claim
38 words
The method of claim 13 , wherein said step c) further comprising the step of: c1) inhibiting the internal refresh operation for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 22
Independent Claim
102 words
A method for refreshing a three-transistor dynamic random access memory (3T-DRAM) sub-array, the method comprising the steps of: a) partitioning a clock cycle into a plurality of time slots; b) assigning each of the time slots to perform a memory cell operation; and c) interleaving an external access operation and an internal refresh operation to the 3T-DRAM sub-array, wherein the internal refresh operation can occur in every clock cycle period, wherein the clock cycle period is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 23
Independent Claim
102 words
A method for refreshing a three-transistor dynamic random access memory (3T-DRAM) sub-array, the method comprising the steps of: a) partitioning a clock cycle into a plurality of time slots; b) assigning each of the time slots to perform a memory cell operation; and c) interleaving an external access operation and an internal refresh operation to the 3T-DRAM sub-array, wherein the internal refresh operation can occur in every clock cycle period, wherein the clock cycle period is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 24
Dependent Claim
40 words
The method of claim 19 , comprising the step of: interpreting an external access command as a read-then-write operation, wherein the external access operation is adapted to be performed as an external read access followed by an external write access.
Claim 25
Dependent Claim
29 words
The method of claim 20 , wherein the internal refresh operation is adapted to be performed as an internal refresh read access followed by an internal refresh write access.
Claim 26
Dependent Claim
31 words
The method of claim 21 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 27
Independent Claim
111 words
A method for accessing a three-transistor dynamic random access memory (3T-DRAM) sub-array, the method comprising the steps of: a) partitioning a clock cycle into a plurality of time slots; b) designating each of the plurality of time slots for performing an array operation for the 3T-DRAM subarray, wherein no idle array time is necessary in the clock cycle; and c) interleaving the array operations of an external access and an internal refresh, wherein the internal refresh can occur in every clock cycle period that is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 28
Independent Claim
111 words
A method for accessing a three-transistor dynamic random access memory (3T-DRAM) sub-array, the method comprising the steps of: a) partitioning a clock cycle into a plurality of time slots; b) designating each of the plurality of time slots for performing an array operation for the 3T-DRAM subarray, wherein no idle array time is necessary in the clock cycle; and c) interleaving the array operations of an external access and an internal refresh, wherein the internal refresh can occur in every clock cycle period that is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 29
Dependent Claim
27 words
The method of claim 23 , wherein the external access operation is adapted to be performed as an external read access followed by an external write access.
Claim 30
Dependent Claim
27 words
The method of claim 24 , wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access.
Claim 31
Dependent Claim
31 words
The method of claim 25 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 32
Dependent Claim
38 words
The method of claim 23 , wherein said step c) further comprising the step of: c1) inhibiting the internal refresh operation for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 33
Independent Claim
138 words
A method for refreshing three-transistor dynamic random access memory (3T-DRAM) cells of a 3T-DRAM sub-array, the method comprising the steps of: a) partitioning a clock cycle into a first plurality of time slots and a second plurality of time slots, the clock cycle beginning with the first time slot of the first plurality of time slots, the clock cycle ending with the last time slot of the second plurality of time slots, wherein the last time slot of the first plurality of time slots overlaps the first time slot of the second plurality of time slots; b) allocating the first plurality of time slots for performing external memory access to a first cell in the 3T-DRAM sub-array; and c) allocating the second plurality of time slots for performing internal refresh to a second cell in the 3T-DRAM sub-array.
Claim 34
Independent Claim
138 words
A method for refreshing three-transistor dynamic random access memory (3T-DRAM) cells of a 3T-DRAM sub-array, the method comprising the steps of: a) partitioning a clock cycle into a first plurality of time slots and a second plurality of time slots, the clock cycle beginning with the first time slot of the first plurality of time slots, the clock cycle ending with the last time slot of the second plurality of time slots, wherein the last time slot of the first plurality of time slots overlaps the first time slot of the second plurality of time slots; b) allocating the first plurality of time slots for performing external memory access to a first cell in the 3T-DRAM sub-array; and c) allocating the second plurality of time slots for performing internal refresh to a second cell in the 3T-DRAM sub-array.
Claim 35
Dependent Claim
28 words
The method of claim 28 , wherein the external memory access operation is adapted to be performed as an external read access followed by an external write access.
Claim 36
Dependent Claim
27 words
The method of claim 29 , wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access.
Claim 37
Dependent Claim
31 words
The method of claim 30 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 38
Dependent Claim
38 words
The method of claim 28 , wherein said step c) further comprising the step of: c1) inhibiting the internal refresh operation for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 39
Independent Claim
161 words
A method for refreshing three-transistor dynamic random access memory (3T-DRAM) cells of a 3T-DRAM sub-array, the method comprising the steps of: a) in a clock cycle, in response to an external access command for a first cell of the sub-array, performing an external access operation that begins with an external read on the first cell; b) in the clock cycle, following completion of the external read, performing external write on the first cell; and c) in the clock cycle, in response to an internal refresh command for a second cell of the sub-array, before completing the external write on the first cell, performing an internal refresh operation on the second cell, wherein both external access operation and the internal refresh operation are performed effectively in one clock cycle period, wherein the clock cycle period is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 40
Independent Claim
161 words
A method for refreshing three-transistor dynamic random access memory (3T-DRAM) cells of a 3T-DRAM sub-array, the method comprising the steps of: a) in a clock cycle, in response to an external access command for a first cell of the sub-array, performing an external access operation that begins with an external read on the first cell; b) in the clock cycle, following completion of the external read, performing external write on the first cell; and c) in the clock cycle, in response to an internal refresh command for a second cell of the sub-array, before completing the external write on the first cell, performing an internal refresh operation on the second cell, wherein both external access operation and the internal refresh operation are performed effectively in one clock cycle period, wherein the clock cycle period is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 41
Dependent Claim
27 words
The method of claim 33 , wherein the external access operation is adapted to be performed as an external read access followed by an external write access.
Claim 42
Dependent Claim
27 words
The method of claim 34 , wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access.
Claim 43
Dependent Claim
31 words
The method of claim 35 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 44
Dependent Claim
38 words
The method of claim 33 , wherein said step c) further comprising the step of: c1) inhibiting the internal refresh operation for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 45
Dependent Claim
144 words
A three-transistor dynamic random access memory (3T-DRAM) sub-array comprising: a sense amplifier (SA); a plurality of 3T-DRAM cells coupled to said SA via a write bit line (WBL) and a read bit line (RBL), wherein of said plurality of cells a first cell that is accessible by a first write word line and a first read word line is coupled to said SA via the WBL and the RBL, wherein of said plurality of cells a second cell that is accessible by a second write word line and a second read word line is coupled to said SA via the WBL and the RBL, and wherein the external access operation of said first cell is interleaved with the internal refresh operation to eliminate clock time devoted exclusively to non-array operation, wherein during non-array operation of the 3T-DRAM sub-array, array operation can also be performed.
Claim 46
Dependent Claim
144 words
A three-transistor dynamic random access memory (3T-DRAM) sub-array comprising: a sense amplifier (SA); a plurality of 3T-DRAM cells coupled to said SA via a write bit line (WBL) and a read bit line (RBL), wherein of said plurality of cells a first cell that is accessible by a first write word line and a first read word line is coupled to said SA via the WBL and the RBL, wherein of said plurality of cells a second cell that is accessible by a second write word line and a second read word line is coupled to said SA via the WBL and the RBL, and wherein the external access operation of said first cell is interleaved with the internal refresh operation to eliminate clock time devoted exclusively to non-array operation, wherein during non-array operation of the 3T-DRAM sub-array, array operation can also be performed.
Claim 47
Dependent Claim
27 words
The 3T-DRAM of claim 38 , wherein the external access operation is adapted to be performed as an external read access followed by an external write access.
Claim 48
Dependent Claim
27 words
The 3T-DRAM of claim 39 , wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access.
Claim 49
Dependent Claim
171 words
A three-transistor dynamic random access memory (3T-DRAM) sub-array comprising: a sense amplifier (SA); a plurality of 3T-DRAM cells coupled to said SA via a write bit line (WBL) and a read bit line (RBL), wherein of said plurality of cells a first cell that is accessible by a first write word line and a first read word line is coupled to said SA via the WBL and the RBL, wherein of said plurality of cells a second cell that is accessible by a second write word line and a second read word line is coupled to said SA via the WBL and the RBL, and wherein the external access operation of said first cell is interleaved with the internal refresh operation to eliminate clock time devoted exclusively to non-array operation, wherein during non-array operation of the 3T-DRAM sub-array, array operation can also be performed, wherein the internal refresh operation is adapted to be inhibited for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 50
Dependent Claim
171 words
A three-transistor dynamic random access memory (3T-DRAM) sub-array comprising: a sense amplifier (SA); a plurality of 3T-DRAM cells coupled to said SA via a write bit line (WBL) and a read bit line (RBL), wherein of said plurality of cells a first cell that is accessible by a first write word line and a first read word line is coupled to said SA via the WBL and the RBL, wherein of said plurality of cells a second cell that is accessible by a second write word line and a second read word line is coupled to said SA via the WBL and the RBL, and wherein the external access operation of said first cell is interleaved with the internal refresh operation to eliminate clock time devoted exclusively to non-array operation, wherein during non-array operation of the 3T-DRAM sub-array, array operation can also be performed, wherein the internal refresh operation is adapted to be inhibited for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 51
Dependent Claim
212 words
A three-transistor dynamic random access memory (3T-DRAM) sub-array comprising: a sense amplifier (SA); a plurality of 3T-DRAM cells coupled to said SA via a write bit line (WBL) and a read bit line (RBL), wherein of said plurality of cells a first cell that is accessible by a first write word line and a first read word line is coupled to said SA via the WBL and the RBL, wherein of said plurality of cells a second cell that is accessible by a second write word line and a second read word line is coupled to said SA via the WBL and the RBL, and wherein the external access operation of said first cell is interleaved with the internal refresh operation to eliminate clock time devoted exclusively to non-array operation, wherein during non-array operation of the 3T-DRAM sub-array, array operation can also be performed, wherein the external access operation is adapted to be performed as an external read access followed by and external write access, wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access, and wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 52
Dependent Claim
212 words
A three-transistor dynamic random access memory (3T-DRAM) sub-array comprising: a sense amplifier (SA); a plurality of 3T-DRAM cells coupled to said SA via a write bit line (WBL) and a read bit line (RBL), wherein of said plurality of cells a first cell that is accessible by a first write word line and a first read word line is coupled to said SA via the WBL and the RBL, wherein of said plurality of cells a second cell that is accessible by a second write word line and a second read word line is coupled to said SA via the WBL and the RBL, and wherein the external access operation of said first cell is interleaved with the internal refresh operation to eliminate clock time devoted exclusively to non-array operation, wherein during non-array operation of the 3T-DRAM sub-array, array operation can also be performed, wherein the external access operation is adapted to be performed as an external read access followed by and external write access, wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access, and wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 53
Dependent Claim
108 words
A 3-transistor dynamic random access memory (3T-DRAM) sub-array comprising: a first memory cell adapted to be activated by a first write word line and a first read word line; and a second cell adapted to be activated by a second write word line and a second read word line, wherein an external access operation on said first cell is interleaved with an internal refresh operation on said second cell, allowing both operations to be performed in one clock cycle period that is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 54
Dependent Claim
108 words
A 3-transistor dynamic random access memory (3T-DRAM) sub-array comprising: a first memory cell adapted to be activated by a first write word line and a first read word line; and a second cell adapted to be activated by a second write word line and a second read word line, wherein an external access operation on said first cell is interleaved with an internal refresh operation on said second cell, allowing both operations to be performed in one clock cycle period that is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 55
Dependent Claim
27 words
The 3T-DRAM of claim 43 , wherein the external access operation is adapted to be performed as an external read access followed by an external write access.
Claim 56
Dependent Claim
27 words
The 3T-DRAM of claim 44 , wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access.
Claim 57
Dependent Claim
31 words
The 3T-DRAM of claim 45 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to the 3T-DRAM sub-array.
Claim 58
Dependent Claim
30 words
The 3T-DRAM of claim 43 , wherein the internal refresh operation is inhibited for the clock cycle in response to the second cell being externally access in the clock cycle.
Claim 59
Dependent Claim
87 words
A three-transistor dynamic random access memory (3T-DRAM) system comprising: a sub-array of 3T-DRAM cells; and a clock generator coupled to said sub-array, said clock generator adapted to issue clock signals for interleaving external access operations and internal refresh operations to said sub-array, wherein one internal refresh operation can be performed in every clock cycle period, wherein the clock cycle period is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 60
Dependent Claim
87 words
A three-transistor dynamic random access memory (3T-DRAM) system comprising: a sub-array of 3T-DRAM cells; and a clock generator coupled to said sub-array, said clock generator adapted to issue clock signals for interleaving external access operations and internal refresh operations to said sub-array, wherein one internal refresh operation can be performed in every clock cycle period, wherein the clock cycle period is less than the time required for consecutively performing the external access operation and thereafter the internal refresh operation upon the completion of the external access operation.
Claim 61
Dependent Claim
28 words
The 3T-DRAM system of claim 48 , wherein the external access operation is adapted to be performed as an external read access followed by an external write access.
Claim 62
Dependent Claim
28 words
The 3T-DRAM system of claim 49 , wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access.
Claim 63
Dependent Claim
31 words
The 3T-DRAM system of claim 50 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to said sub-array.
Claim 64
Dependent Claim
36 words
The 3T-DRAM system of claim 48 , wherein an internal refresh operation to a cell of said sub-array is inhibited for a clock cycle in response to said cell being externally access in the clock cycle.
Claim 65
Dependent Claim
146 words
A DRAM system comprising: a sub-array comprising a first cell and a second cell; a first write word line and a first read word line coupled to said first cell for the array operation of enabling said first cell for accepting external access and internal refresh; a second write word line and a second read word line coupled to said second cell for the array operation of enabling said second cell for accepting external access and internal refresh; a clock generator coupled to said sub-array, said clock generator adapted to issue clock signals for interleaving an external access operation to said first cell and an internal refresh operation to said second cell by performing array operations while non-array operations are being performed, wherein idle time for said write word line and said read word line is effectively eliminated by not waiting for completion of non-array operations.
Claim 66
Dependent Claim
146 words
A DRAM system comprising: a sub-array comprising a first cell and a second cell; a first write word line and a first read word line coupled to said first cell for the array operation of enabling said first cell for accepting external access and internal refresh; a second write word line and a second read word line coupled to said second cell for the array operation of enabling said second cell for accepting external access and internal refresh; a clock generator coupled to said sub-array, said clock generator adapted to issue clock signals for interleaving an external access operation to said first cell and an internal refresh operation to said second cell by performing array operations while non-array operations are being performed, wherein idle time for said write word line and said read word line is effectively eliminated by not waiting for completion of non-array operations.
Claim 67
Dependent Claim
28 words
The 3T-DRAM system of claim 53 , wherein the external access operation is adapted to be performed as an external read access followed by an external write access.
Claim 68
Dependent Claim
28 words
The 3T-DRAM system of claim 54 , wherein the internal refresh operation is adapted to be performed as an internal read access followed by an internal write access.
Claim 69
Dependent Claim
31 words
The 3T-DRAM system of claim 55 , wherein the internal refresh write can be extended to a next clock cycle before a next external read operation is performed to said sub-array.
Claim 70
Dependent Claim
38 words
The DRAM system of claim 53 , wherein in response to receiving an external access command for said second cell in a clock cycle, the internal refresh operation of said second cell is inhibited in the clock cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-10-26 | 2008-04-26 | 2008-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-10-26 | 2012-04-26 | 2012-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-10-26 | 2016-04-26 | 2016-10-26 | $7700.00 | Window Closed / Lapsed |