US7282978B2
Expired / Lapsed
US
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Duty cycle correction device
Assignee: SK Hynix Inc
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Filing: 2006-06-29
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Granted: 2007-10-16
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Expires: 2026-06-29
Abstract
Abstract Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) device by using a phase mixer. The duty cycle correction device comprises: a mixer for receiving a first clock signal and a second clock signal and outputting a first signal; a phase splitter for receiving the first signal and outputting a third clock signal by delaying the first signal and a fourth clock signal by delaying and inverting the first signal; a duty detection unit for receiving the third and fourth clock signals and detecting a difference between their duty cycles; a combination unit for outputting a second signal; and a shift register for outputting a control signal to adjust a mixing ratio of the first and second clock signals in response to the second signal.
Inventors
- 👤 Hyun Woo Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:49
CPC Classifications
G; G11; G11C; G11C8/00; H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C8/04; H03K5/13; H03K2005/00013; H03K2005/00019; H03K2005/00026; H03K2005/00052; H03K2005/00058
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
184 words
A duty cycle correction device comprising: a mixer receiving a first clock signal and a second clock signal, and mixing phases of the first and second clock signals according to a digital control signal having logic, thereby outputting a first signal; a phase splitter receiving the first signal, and outputting a third clock signal by delaying the first signal for a predetermined period of time and a fourth clock signal by delaying and inverting the first signal for a predetermined period of time; a duty detection unit receiving the third and fourth clock signals, and detecting a difference between duty cycles of the third and fourth clock signals; a combination unit outputting a second signal, by combining an output signal of the duty detection unit and previously-stored output signals; and a shift register generating the digital control signal having the logic values corresponding to a logical level of the second signal and outputting the digital control signal to adjust a mixing ratio of the first and second clock signals, which are applied to the mixer, in response to the first and second clock signal.
Claim 2
Dependent Claim
184 words
A duty cycle correction device comprising: a mixer receiving a first clock signal and a second clock signal, and mixing phases of the first and second clock signals according to a digital control signal having logic, thereby outputting a first signal; a phase splitter receiving the first signal, and outputting a third clock signal by delaying the first signal for a predetermined period of time and a fourth clock signal by delaying and inverting the first signal for a predetermined period of time; a duty detection unit receiving the third and fourth clock signals, and detecting a difference between duty cycles of the third and fourth clock signals; a combination unit outputting a second signal, by combining an output signal of the duty detection unit and previously-stored output signals; and a shift register generating the digital control signal having the logic values corresponding to a logical level of the second signal and outputting the digital control signal to adjust a mixing ratio of the first and second clock signals, which are applied to the mixer, in response to the first and second clock signal.
Claim 3
Dependent Claim
29 words
The duty cycle correction device of claim 1 , wherein a rising edge of the first clock signal is synchronized with a rising edge of the second clock signal.
Claim 4
Dependent Claim
134 words
The duty cycle correction device of claim 1 , wherein the mixer comprises: a first inverter group having N inverters, which are connected in parallel between a first node and a second node; a second inverter group having N inverters, which are connected in parallel between a third node and the second node; a buffer means connected between the second node and a fourth node, wherein the first clock signal is applied to the first node; the second clock signal is applied to the third node; the first signal is output through the fourth node; and a part of inverters included in the first and second inverter groups are enabled or disabled by the digital control signal output from the shift register, thereby adjusting the mixing ratio of the first and second clock signals.
Claim 5
Dependent Claim
91 words
The duty cycle correction device of claim 1 , wherein the phase splitter comprises: an even number of inverters connected in serial to each other, so as to receive the first signal and to output the third clock signal by delaying the received first signal for a predetermined period of time; and an odd number of inverters connected in serial to each other, so as to receive the first signal and to output the fourth clock signal by delaying and inverting the received first signal for a predetermined period of time.
Claim 6
Dependent Claim
35 words
The duty cycle correction device of claim 1 , wherein the duty detection unit detects a difference between a high-level section of the third clock signal and a high-level section of the fourth clock signal.
Claim 7
Dependent Claim
174 words
A duty cycle correction device comprising: a mixer receiving a first clock signal and a second clock signal, and mixing phases of the first and second clock signals according to a digital control signal having logic values, thereby outputting a first signal; an output circuit receiving the first signal, and outputting a third clock signal by delaying the first signal for a predetermined period of time and a fourth clock signal by delaying and inverting the first signal for a predetermined period of time; a duty detection unit receiving the third and fourth clock signals of the output circuit, and detecting a difference between duty cycles of the third and fourth clock signals; a combination unit outputting a second signal, by combining an output signal of the duty detection unit and previously-stored output signals; and a shift register generating the digital control signal having the logic values corresponding to a logical level of the second signal and outputting the digital control signal to adjust a mixing ratio of the first and second clock signals.
Claim 8
Dependent Claim
174 words
A duty cycle correction device comprising: a mixer receiving a first clock signal and a second clock signal, and mixing phases of the first and second clock signals according to a digital control signal having logic values, thereby outputting a first signal; an output circuit receiving the first signal, and outputting a third clock signal by delaying the first signal for a predetermined period of time and a fourth clock signal by delaying and inverting the first signal for a predetermined period of time; a duty detection unit receiving the third and fourth clock signals of the output circuit, and detecting a difference between duty cycles of the third and fourth clock signals; a combination unit outputting a second signal, by combining an output signal of the duty detection unit and previously-stored output signals; and a shift register generating the digital control signal having the logic values corresponding to a logical level of the second signal and outputting the digital control signal to adjust a mixing ratio of the first and second clock signals.
Claim 9
Dependent Claim
29 words
The duty cycle correction device of claim 6 , wherein a rising edge of the first clock signal is synchronized with a rising edge of the second clock signal.
Claim 10
Dependent Claim
134 words
The duty cycle correction device of claim 6 , wherein the mixer comprises: a first inverter group having N inverters, which are connected in parallel between a first node and a second node; a second inverter group having N inverters, which are connected in parallel between a third node and the second node; and a buffer means connected between the second node and a fourth node; wherein the first clock signal is applied to the first node, the second clock signal is applied to the third node, the first signal is output through the fourth node, and a part of inverters including the first and second inverter groups are enabled or disabled by the digital control signal output from the shift register, thereby adjusting the mixing ratio of the first and second clock signals.
Claim 11
Dependent Claim
91 words
The duty cycle correction device of claim 6 , wherein the output circuit comprises: an even number of inverters connected in serial to each other, so as to receive the first signal and to output the third clock signal by delaying the received first signal for a predetermined period of time; and an odd number of inverters connected in serial to each other, so as to receive the first signal and to output the fourth clock signal by delaying and inverting the received first signal for a predetermined period of time.
Claim 12
Dependent Claim
35 words
The duty cycle correction device of claim 6 , wherein the duty detection unit detects a difference between a high-level section of the third clock signal and a high-level section of the fourth clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-10-15 | 2011-04-16 | 2011-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-10-15 | 2015-04-16 | 2015-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-10-15 | 2019-04-16 | 2019-10-16 | $7700.00 | Window Closed / Lapsed |